Yet Another Gamecube Documentation

5 Hardware Registers

5.1 CP - Command Processor

Registerblock Base	Size of Registerblock	common access size
`0xcc000000`	`0x80`	`2`

0xCC000000 2 R/W SR - Status Register

`15`	`8`	`7`	`0`

bit(s)		description
5-15		unused/reserved
4		BP (breakpoint?) interrupt
3		GP is idle for commands (1: idle)
2		GP is idle for reading (1: idle)
1		gx fifo underflow (ptr<lo watermark)
0		gx fifo overflow (ptr>hi watermark)

0xCC000002 2 R/W CR - Control Register

`15`	`8`	`7`	`0`
		`..bl`	`.mig`

bit(s)		description
6-15		unused/reserved
5	b	bp enable
4	l	gp link enable (enable for linking of cp/pe FIFO)
3		FIFO underflow irq enable (?)
2	m	FIFO overflow irq enable? / cp irq (clear to acknowledge) ?
1	i	cp irq enable (?) (write 1 to clear bp irq?)
0	g	gp FIFO read enable

0xCC000004 2 W Clear Register

bit(s)		description
2-15		unused/reserved
1		write 1 to clear FIFO underflow
0		write 1 to clear FIFO overflow

0xCC00000E 2 R/W token register

0xCC000010 2 R/W bounding box - left

0xCC000012 2 R/W bounding box - right

0xCC000014 2 R/W bounding box - top

0xCC000016 2 R/W bounding box - bottom

0xCC000020 2 R/W cp FIFO base lo

0xCC000022 2 R/W cp FIFO base hi

0xCC000024 2 R/W cp FIFO end lo

0xCC000026 2 R/W cp FIFO end hi

0xCC000028 2 R/W cp FIFO high watermark lo

0xCC00002a 2 R/W cp FIFO high watermark hi

0xCC00002c 2 R/W cp FIFO low watermark lo

0xCC00002e 2 R/W cp FIFO low watermark hi

the low and high watermark control the assertion of the CP interrupt

0xCC000030 2 R/W cp FIFO read/write distance lo

0xCC000032 2 R/W cp FIFO read/write distance hi

0xCC000034 2 R/W cp FIFO write pointer lo

0xCC000036 2 R/W cp FIFO write pointer hi

0xCC000038 2 R/W cp FIFO read pointer lo

0xCC00003a 2 R/W cp FIFO read pointer hi

0xCC00003c 2 R/W cp FIFO bp lo

0xCC00003e 2 R/W cp FIFO bp hi

index

5.1.1 Token register

You can insert this dirty marker, at the end of command list, by this way :

*(u32 *)GXFIFO = 0x4800XXXX
*(u32 *)GXFIFO = 0x4700XXXX

Where XXXX is the token value. When command processor reaches this stage, it writes XXXX into PE token register (see above), and then raise "PE TOKEN" interrupt. Thus you can monitor the completion of your drawing tasks.

note: its probably a good idea to send a BP 'drawing complete' command (0x45000002) before the insertion of the token.

index

5.2 PE - Pixel Engine

Registerblock Base	Size of Registerblock	common access size
`0xcc001000`	`0x100`	`2`

0xcc001000 2 R/W Z configuration

`15`	`8`	`7`	`0`

bit(s)		description
4		Z update enable
1-3		function
0		z-comperator enable

0xcc001002 2 R/W Alpha configuration

`15`	`8`	`7`	`0`

bit(s)		description
12-15		blend operator (?)
11		substractive / additive toggle (?)
8-10		source
5-7		destination
4		alpha update enable
3		color update enable
2		dither enable (?)
1		arithmetic blending enable (?)
0		boolean blending enable (?)

0xcc001004 2 R/W destination alpha

`15`	`8`	`7`	`0`

bit(s)		description
8		enable
0-7		alpha

0xcc001006 2 R/W Alpha Mode

`15`	`8`	`7`	`0`

bit(s)		description
8-15		mode
0-7		threshold

0xcc001008 2 R/W Alpha Read (?)

`15`	`8`	`7`	`0`

bit(s)		description
		mode
2		?

0xcc00100a 2 R/W Interrupt Status Register

`15`	`8`	`7`	`0`

bit(s)		description
3		PE Finish (set to acknowledge)
2		PE Token (set to acknowledge)
1		PE Finish enable (?)
0		PE Token enable (?)

0xcc00100e 2 R/W PE Token ?

`15`	`8`	`7`	`0`
`tttt`	`tttt`	`tttt`	`tttt`

bit(s)		description
0-15	t	PE Token (asserted from last PE Token Interrupt)

index

5.3 VI - Video Interface

Registerblock Base	Size of Registerblock	common access size
`0xcc002000`	`0x100`	`4`

0xCC002000 2 R/W VTR - Vertical Timing Register

`15`	`8`	`7`	`0`
`00aa`	`aaaa`	`aaaa`	`eeee`

bit(s)		description
4-13	a	ACV - Active Video (in full Lines) ? other source says halflines
0-3	e	EQU - Equalization pulse in half lines

pal50/pal60/ntsc: 0x11F5, 0x0F06, 0x0F06

The value in ACV is double buffered

0xCC002002 2 R/W DCR - Display Configuration Register

`15`	`8`	`7`	`0`
`0000`	`00pp`	`lltt`	`dire`

bit(s)

description

FMT - Current Video Format

0	NTSC
1	PAL
2	MPAL
3	Debug

LE1 - Enables Display Latch 1

0	Off
1	On for 1 field
2	On for 2 fields
3	Always On

LE0 - Enables Display Latch 0

0	Off
1	On for 1 field
2	On for 2 fields
3	Always On

DLR - Selects 3D Display Mode

NIN - Interlace Selector

0	Interlaced
1	Non-Interlaced, top field drawn at field rate and bottom field is not displayed

RST - Reset - Clears all data requests and puts VI into its idle state.

ENB - Enable - Enables video timing generation and data request.

pal50/pal60/ntsc: 0x0101, 0x0001, 0x0001

0xCC002004 4 R/W HTR0 - Horizontal Timing 0

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`0sss`	`ssss`	`0eee`	`eeee`	`0000`	`000w`	`wwww`	`wwww`

bit(s)		description
	s	HCS - Horizontal Sync Start to Color Burst Start
	e	HCE - Horizontal Sync Start to Color Burst End
	w	HLW - Halfline Width (W*16 = Width (720))

pal50/pal60/ntsc: 0x4B6A01B0, 0x476901AD, 0x476901AD

0xCC002008 4 R/W HTR1 - Horizontal Timing 1

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`0000`	`0sss`	`ssss`	`ssse`	`eeee`	`eeee`	`ewww`	`wwww`

bit(s)		description
	s	HBS - Half line to horizontal blanking start
	e	HBE - Horizontal Sync Start to horizontal blank end
	w	HSY - Horizontal Sync Width

pal50/pal60/ntsc: 0x02F85640, 0x02EA5140, 0x02EA5140

Setting bit 0 seems to blackout the screen. (Similar to ViBlack?)

0xCC00200C 4 R/W VTO - Odd Field Vertical Timing Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`..ss`	`ssss`	`ssss`	`....`	`..rr`	`rrrr`	`rrrr`

bit(s)		description
`16-25`	s	PSB - Post blanking in half lines
`0-9`	r	PRB - Pre-blanking in half lines

pal50/pal60/ntsc: 0x00010023, 0x00030018, 0x00030018

This register sets up the pre-blanking and post-blanking interval of odd fields, PRB and PSB are double-buffered.

0xCC002010 4 R/W VTE - Even Field Vertical Timing Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`..ss`	`ssss`	`ssss`	`....`	`..rr`	`rrrr`	`rrrr`

bit(s)		description
`16-25`	s	PSB - post-blanking in halflines
`0-9`	r	PRB - pre-blanking in halflines

pal50/pal60/ntsc: 0x00000024, 0x00020019, 0x00020019

This register sets up the pre-blanking and post-blanking intervals of even fields. PRB and PSB are double-buffered.

0xCC002014 4 R/W BBEI - Odd Field Burst Blanking Interval Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
21-31		BE3 - Field 3 start to burst blanking end in halflines
16-20		BS3 - Field 3 start to burst blanking start in halflines
5-15		BE1 - Field 1 start to burst blanking end in halflines
0-4		BS1 - Field 1 start to burst blanking start in halflines

pal50/pal60/ntsc: 0x4D2B4D6D, 0x410C410C, 0x410C410C

0xCC002018 4 R/W BBOI - Even Field Burst Blanking Interval Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
21-31		BE4 - Field 4 start to burst blanking end in halflines
16-20		BS4 - Field 4 start to burst blanking start in halflines
5-15		BE2 - Field 2 start to burst blanking end in halflines
0-4		BS2 - Field 2 start to burst blanking start in halflines

pal50/pal60/ntsc: 0x4D8A4D4C, 0x40ED40ED, 0x40ED40ED

0xCC00201c 4 R/W TFBL - Top Field Base Register (L) (External Framebuffer Half 1)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`yyy?`	`zzzz`	`aaaa`	`aaaa`	`aaaa`	`aaax`	`xxxx`	`xxxx`

bit(s)		description
29-31	y	always zero (maybe some write only control register stuff?, setting bit 31 clears bits 31-28 (?))
28		page offset bit (*1)
24-27	z	XOF - Horizontal Offset of the left-most pixel within the first word of the fetched picture.
9-23	a	FBB - bit 23 - bit 9 of XFB Address (*2)
0-8	x	unused (?)

pal50/pal60/ntsc: 0x00435A4E, 0x00435A4E, 0x00435A4E

This register specifies the display origin of the top field of a picture in 2D mode or for the left picture in 3D mode

(*1) when this bit is set, the framebuffer address is calculated as (address> >5)
(*2) if bit 28 is cleared, highest possible Address: 0x80fffe00 (set register to 0x00fffe00) (aligned to 9bit)

0xCC002020 4 R/W TFBR - Top Field Base Register (R) (Only valid in 3D Mode)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`0000`	`0000`	`ffff`	`ffff`	`ffff`	`fff0`	`0000`	`0000`

bit(s)		description
	f	FBB - External Memory Address of frame buffer

pal50/pal60/ntsc: 0x00000000, 0x00000000, 0x00000000

This register specifies the base address of the top field for the right picture in 3D mode.

0xCC002024 4 R/W BFBL - Bottom Field Base Register (L) (External Framebuffer Half 2)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`yyyy`	`yyyy`	`aaaa`	`aaaa`	`aaaa`	`aaax`	`xxxx`	`xxxx`

bit(s)		description
	y	always zero (maybe some write-only control register stuff?)
28		page offset bit (*1)
	a	FBB - bit 23 - bit 9 of XFB Address
	x	unused (?)

pal50/pal60/ntsc: 0x00435A4E, 0x00435A4E, 0x00435A4E

This register specifies the display origin of the bottom field of a picture in 2D mode or for the left picture in 3D mode

(*1) when this bit is set, the framebuffer address is calculated as (address> >5)

0xCC002028 4 R/W BFBR - Bottom Field Base Register (R) (Only valid in 3D Mode)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`0000`	`0000`	`ffff`	`ffff`	`ffff`	`fff0`	`0000`	`0000`

bit(s)		description
	f	FBB - External Memory Address of frame buffer

pal50/pal60/ntsc: 0x00000000, 0x00000000, 0x00000000

specifies the base address of the bottom field for the right picture in 3D mode.

0xCC00202C 2 R DPV - current vertical Position

`15`	`8`	`7`	`0`
`0000`	`0vvv`	`vvvv`	`vvvv`

bit(s)		description
	v	VCT - current vertical Position of Raster beam

pal50/pal60/ntsc: 0x013C, 0x0005, 0x0000

0xCC00202E 2 R DPH - current horizontal Position (?)

`15`	`8`	`7`	`0`
`0000`	`0hhh`	`hhhh`	`hhhh`

bit(s)		description
	h	HCT - current horizontal Position of Raster beam (?)

pal50/pal60/ntsc: 0x0144, 0x0176, 0x0000

The Horizontal Count is in pixels and runs from 1 to # pixels per line. It is reset to 1 at the beginning of every line. The Vertical Count is in lines (on a frame basis) and runs from 1 to # lines per frame. It is 1 at the beginning of pre-equalization. This is a frame line count. So for example: for NTSC vcount=264 is the first (full) line in the second field and vcount=525 is the last line in the frame (fields being numbered 1-4). For non-interlaced modes vcount is on a field-by-field basis (for NTSC vcount ranges from 1-263). This counting scheme applies the Display Position, Display Interrupt, and Display Latch registers.

0xCC002030 4 R/W DI0 - Display Interrupt 0

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`i00e`	`00vv`	`vvvv`	`vvvv`	`0000`	`00hh`	`hhhh`	`hhhh`

bit(s)		description
31	i	INT - Interrupt Status (1=Active) (Write to clear)
28	e	ENB - Interrupt Enable Bit
16-25	v	VCT - Vertical Position
0-9	h	HCT - Horizontal Position

pal50/pal60/ntsc: 0x113901B1, 0x110701AE, 0x110701AE

There are a total of four display interrupt registers (0-3). They are used to generate interrupts to the main processor at different positions within a field. Each register has a separate enable bit. The interrupt is cleared by writing a zero to the status flag (INT).

0xCC002034 4 R/W DI1 - Display Interrupt 1

pal50/pal60/ntsc: 0x10010001, 0x10010001, 0x10010001

Refer to Display Interrupt 0

0xCC002038 4 R/W DI2 - Display Interrupt 2

pal50/pal60/ntsc: 0x00010001, 0x00010001, 0x00010001

Refer to Display Interrupt 0

0xCC00203C 4 R/W DI3 - Display Interrupt 3

pal50/pal60/ntsc: 0x00010001, 0x00010001, 0x00010001

Refer to Display Interrupt 0

0xCC002040 4 R/W DL0 - Display Latch Register 0

bit(s)		Description
`31`		TRG - Trigger Flag
`16-26`		VCT - Vertical Count
`0-10`		HCT - Horizontal Count

pal50/pal60/ntsc: 0x0000, 0x0000, 0x0000

The Display Latch Register 0 latches the value of the Display Position Register at the rising edge of the gt0 signal. The trigger flag is set if a gun trigger is detected. Writing a zero to the register clears the trigger flag.

0xCC002044 4 R/W DL1 - Display Latch Register 1

pal50/pal60/ntsc: 0x0000, 0x0000, 0x0000

See the description of Display Latch Register 0. This register is latched on the rising edge of the gt1 signal.

0xCC002048 2 R/W HSW - Scaling Width Register

`15`	`8`	`7`	`0`

bit(s)		description
0-9		SRCWIDTH - Horizontal Stepping size

pal50/pal60/ntsc: 0x2850, 0x2850, 0x2850

This register is the number of source pixels to be scaled. This is only used when the Horizontal Scaler is enabled. For example, if the image is to be scaled from 320x240 to 640x240, 320 would be written into this register.

0xCC00204a 2 R/W HSR - Horizontal Scaling Register

`15`	`8`	`7`	`0`
`000e`	`000v`	`vvvv`	`vvvv`

bit(s)		description
12	e	HS_EN - Enable Horizontal Scaling
0-8	v	STP - Horizontal stepping size (U1.8 Scaler Value) (0x160 Works for 320)

pal50/pal60/ntsc: 0x0100, 0x0100, 0x0100

This register sets up the step size of the horizontal stepper.

0xCC00204C 4 R/W FCT0 - Filter Coefficient Table 0 (AA stuff)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
20-29		T2 - Tap2
10-19		T1 - Tap1
0-9		T0 - Tap0

pal50/pal60/ntsc: 0x1AE771F0, 0x1AE771F0, 0x1AE771F0

sets up part of the low-pass filter. Taps 0 to 9 are in the range (0.0, 2.0)

0xcc002050 4 R/W FCT1 - Filter Coefficient Table 1 (AA stuff)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
20-29		T5 - Tap5
10-19		T4 - Tap4
0-9		T3 - Tap3

pal50/pal60/ntsc: 0x0DB4A574, 0x0DB4A574, 0x0DB4A574

0xcc002054 4 R/W FCT2 - Filter Coefficient Table 2 (AA stuff)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
20-29		T8 - Tap8
10-19		T7 - Tap7
0-9		T6 - Tap6

pal50/pal60/ntsc: 0x00C1188E, 0x00C1188E, 0x00C1188E

sets up part of the low-pass filter

0xcc002058 4 R/W FCT3 - Filter Coefficient Table 3 (AA stuff)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24-31		T12 - Tap12
16-23		T11 - Tap11
8-15		T10 - Tap10
0-7		T9 - Tap9

pal50/pal60/ntsc: 0xC4C0CBE2, 0xC4C0CBE2, 0xC4C0CBE2

sets up part of the low-pass filter. Taps 9 to tap 24 are in the Rage (-0.125, 0.125)

0xcc00205c 4 R/W FCT4 - Filter Coefficient Table 4 (AA stuff)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24-31		T16 - Tap16
16-23		T15 - Tap15
8-15		T14 - Tap14
0-7		T13 - Tap13

pal50/pal60/ntsc: 0xFCECDECF, 0xFCECDECF, 0xFCECDECF

0xcc002060 4 R/W FCT5 - Filter Coefficient Table 5 (AA stuff)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24-31		T20 - Tap20
16-23		T19 - Tap19
8-15		T18 - Tap18
0-7		T17 - Tap17

pal50/pal60/ntsc: 0x13130F08, 0x13130F08, 0x13130F08

0xcc002064 4 R/W FCT6 - Filter Coefficient Table 6 (AA stuff)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24-31		T24 - Hardwired to zero
16-23		T23 - Tap23
8-15		T22 - Tap22
0-7		T21 - Tap21

pal50/pal60/ntsc: 0x00080C0F, 0x00080C0F, 0x00080C0F

sets up part of the low-pass filter

0xcc002068 4 R/W ? (AA stuff)

pal50/pal60/ntsc: 0x00FF0000, 0x00FF0000, 0x00FF0000

0xCC00206C 2 R/W VICLK - VI Clock Select Register

`15`	`8`	`7`	`0`
`0000`	`0000`	`0000`	`000s`

bit(s)

description

0	27 MHz video CLK
1	54 MHz video CLK (used in Progressive Mode)

pal50/pal60/ntsc: 0x0000, 0x0000, 0x0000

0xCC00206e 2 R/W VISEL - VI DTV Status Register

`15`	`8`	`7`	`0`

bit(s)		description
2		VISEL - don't care

pal50/pal60/ntsc: 0x0000, 0x0000, 0x0000

this register allows software to read the status of two i/o pins

0xCC002070 2 R/W ?

Holds 0x280, but has no effect on change (maybe for Progressive ?)

pal50/pal60/ntsc: 0x0280, 0x0280, 0x0280

0xCC002072 2 r/w HBE - Border HBE

`15`	`8`	`7`	`0`

bit(s)		description
15		BRDR_EN - Border Enable
0-9		HBE656 - Border Horizontal Blank End

pal50/pal60/ntsc: 0x0000, 0x0000, 0x0000

This register (in conjunction with the border HBS) sets up a black border around the actual active pixels in debug mode. This was done in order to accommodate certain encoders that only support 720 active pixels. The border HBE and HBS can be programmed for 720 active pixels while the regular HBE and HBS can be programmed to the actual active width. This allows the frame buffer to be of any width without having to manually set up a border in memory. These registers will only take effect if enabled and in debug mode.

0xcc002074 2 r/w HBS - Border HBS

`15`	`8`	`7`	`0`

bit(s)		description
0-9		HBS656 - Border Horizontal Blank start

pal50/pal60/ntsc: 0x0000, 0x0000, 0x0000

0xcc002076 2 ?/? ? (unused?)

pal50/pal60/ntsc: 0x00FF, 0x00FF, 0x00FF

0xcc002078 4 ?/? ? (unused?)

pal50/pal60/ntsc: 0x00FF00FF, 0x00FF00FF, 0x00FF00FF

0xcc00207c 4 ?/? ? (unused?)

pal50/pal60/ntsc: 0x00FF00FF 0x00FF00FF, 0x00FF00FF

index

5.3.1 Video Modes

Mode	TV Norm / Region	Framerate	Columns	Lines
NTSC	ntsc (usa, japan)	60Hz	640	480
PAL	pal (europe)	50Hz	640	574
DEBUG
DEBUG PAL
MPAL	pal (brazil)	60Hz	640	480
PAL60	pal	60Hz	640	480

note: other modes may be possible using VGA output, although its unlikely.

index

5.4 PI - Processor Interface

Registerblock Base	Size of Registerblock	common access size
`0xcc003000`	`0x100`	`4`

0xCC003000 4 r INTSR - interrupt cause

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`...r`	`....`	`....`	`....`	`....`

bit			Description
17-31			unused/reserved
16	r	RSWST	Reset Switch State (1 when pressed)
14-15			unused/reserved
13		HSP	High Speed Port
12		DEBUG	External Debugger
11		CP	Command FIFO
10		PE FINISH	Frame is Ready
9		PE TOKEN	Token Assertion in Command List
8		VI	Video Interface
7		MEM	Memory Interface
6		DSP	DSP
5		AI	Streaming
4		EXI	EXI
3		SI	Serial
2		DI	DVD
1		RSW	Reset Switch
0		ERROR	GP runtime error

0xCC003004 4 r/w INTMR - interrupt mask

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`....`

bit		Description
13	HSP	High Speed Port
12	DEBUG	External Debugger
11	CP	Command FIFO
10	PE FINISH	Frame is Ready
9	PE TOKEN	Token Assertion in Command List
8	VI	Video Interface
7	MEM	Memory Interface
6	DSP	DSP
5	AI	Streaming
4	EXI	EXI
3	SI	Serial
2	DI	DVD
1	RSW	Reset Switch
0	ERROR	GP runtime error

0xCC00300c 4 r/w FIFO Base Start

0xCC003010 4 ?/? FIFO Base End?

0xCC003014 4 ?/? PI (cpu) FIFO current Write Pointer?

0xCC003018 4 ?/? ?

0xCC00301c 4 ?/? ?

0xCC003020 4 ?/? ?

0xCC003024 4 ?/? Reset?

Writing anything here seems to cause a complete reset.

0xCC00302c 4 ?/? ?

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`....`

bit(s)		Description
28-31		console type (2: hw2)

index

5.4.1 Operation

5.4.1.1 FIFO/Write Gather Pipe when CPU writes a byte to 0xcc008000, it is written to mem[writeptr], and writeptr is increased automatically.

0xcc008000 is the write gather pipe, a way for the CPU to blast sequences of things of various sizes to memory without having to keep track of the write pointer and wrapping manually. the gp then reads what the CPU has written to memory. It is used for Display Lists. it will disconnect the GP from the writegatherpipe (cc000002 & 0x10 = 0), and change the write ptr to where it wants to write a display list.. then use ordinary GX commands to build it. there's a Call Displaylist GX command.. so it will store render commands for rendering a certain object (for example) in a display list in memory, then send the CallDL with the address to the list instead of sending all the vertices over the FIFO.

5.4.1.2 Interrupts

Each interrupt has one or more "source" devices. It means that some kind of device may generate a couple of different interrupts, represented by a single bit in interrupt registers. To "enable" interrupt, set bit in mask register. To ignore all interrupts write 0 to interrupt mask register. Raising of any interrupt will set corresponding bit in interrupt cause register. Interrupt cause register resets to 0, when read (i.e. you must read it to clear pending interrupts).

Interrupt mask register isn't controlled by hardware logic. Note that masking of interrupt in INTMR doesn't disable it at all. It is only causing masked interrupt to be ignored in the software interrupt handler. You must clear corresponding "source" device registers, to completely disable interrupt.

5.4.1.3 hotreset

this code snippet will reset the machine almost as if powered off/on

        lis r3,0
        lis r9,0xCC00
        sth r3, 0x2000(r9)
        li r4, 3
        stw r4, 0x3024(r9)
        stw r3, 0x3024(r9)
        nop
loop__:
        b loop__

index

5.5 MI - Memory Interface

Protection can be enabled only for pages (page size is 1024 bytes), and you can specify only 4 protected regions of memory. External interrupt will be raised, if CPU try to wrong access in protected region. Because it's allowed to enable protection for 4 regions only, there are a total of 4 possible interrupts which are called MEM_0, MEM_1, MEM_2 and MEM_3.

Registerblock Base	Size of Registerblock	common access size
`0xcc004000`	`0x80`	`4`

0xCC004000 4 r/w Protected Region No1

0xCC004004 4 r/w Protected Region No2

0xCC004008 4 r/w Protected Region No3

0xCC00400c 4 r/w Protected Region No4

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`llll`	`llll`	`llll`	`llll`	`hhhh`	`hhhh`	`hhhh`	`hhhh`

bit(s)		Description
16-31	l	Page Address Lo
0-15	h	Page Address Hi

note: the page address can be calculated as (physical_address> >10)

0xCC004010 2 r/w type of the protection, 4*2 bits

`15`	`8`	`7`	`0`
`....`	`....`	`3322`	`1100`

bit(s) Description

unused/reserved

6 3 Channel 3

`0`	access denied
`1`	read only (break on write)
`2`	write only (break on read)
`3`	read / write (no protection, full access)

4 2 Channel 2 (see Channel 3)

2 1 Channel 1 (see Channel 3)

0 0 Channel 0 (see Channel 3)

0xCC00401c 2 ?/w MI interrupt mask

`15`	`8`	`7`	`0`
`....`	`....`	`...m`	`3210`

bit(s)		Description
4	m	mask all MI interrupts (1 - enable)
3	3	mask MEM3 interrupt (1 - enable)
2	2	mask MEM2 interrupt (1 - enable)
1	1	mask MEM1 interrupt (1 - enable)
0	0	mask MEM0 interrupt (1 - enable)

0xCC00401e 2 r/w interrupt cause

`15`	`8`	`7`	`0`
`....`	`....`	`...m`	`3210`

bit(s)

Description

all MI interrupts

MEM3 interrupt

read	0	irq has not been requested
	1	irq has been requested
write	0	no effect
	1	clear pending irq assertion

MEM2 interrupt

read	0	irq has not been requested
	1	irq has been requested
write	0	no effect
	1	clear pending irq assertion

MEM1 interrupt

read	0	irq has not been requested
	1	irq has been requested
write	0	no effect
	1	clear pending irq assertion

MEM0 interrupt

read	0	irq has not been requested
	1	irq has been requested
write	0	no effect
	1	clear pending irq assertion

0xCC004020 2 ?/? ?

`15`	`8`	`7`	`0`
`....`	`....`	`....`	`..m.`

bit(s)		Description
1	1	? (set when MI interrupt has been asserted)
0	0	?

note: assume to be zero, after init, and should be cleared by interrupt handler.

0xCC004022 2 r/? ADDRLO - address which failed protection rules

`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`

bit(s)		Description
5-15		bit 5-bit 15 of address
0-4		zero

0xCC004024 2 r/? ADDRHI - address, which failed protection rules

`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`

bit(s)		Description
14-15		zero
0-13		bit 16-bit 29 of address

0xCC004032 2 r/? TIMERHI

0xCC004034 2 r/? TIMERLO

0xCC004036 2 r/? TIMERHI

0xCC004038 2 r/? TIMERLO

0xCC00403a 2 r/? TIMERHI

0xCC00403c 2 r/? TIMERLO

0xCC00403e 2 r/? TIMERHI

0xCC004040 2 r/? TIMERLO

0xCC004042 2 r/? TIMERHI

0xCC004044 2 r/? TIMERLO

0xCC004046 2 r/? TIMERHI

0xCC004048 2 r/? TIMERLO

0xCC00404a 2 r/? TIMERHI

0xCC00404c 2 r/? TIMERLO

0xCC00404e 2 r/? TIMERHI

0xCC004050 2 r/? TIMERLO

0xCC004052 2 r/? TIMERHI

0xCC004054 2 r/? TIMERLO

0xCC004056 2 r/? TIMERHI

0xCC004058 2 r/? TIMERLO

note: writing anything to the timer register resets it to zero

0xCC00405a 2 r/? ?

`15`	`8`	`7`	`0`
`....`	`.xxx`	`xxxx`	`xxxx`

bit(s)		Description
11-15		unused ?

index

5.6 DSP - Digital Signal Processor Interface

At the heart of the GCN audio hardware is a custom digital signal processor (DSP) which is largely dedicated to pitch modulation and the mixing of voices and effects data. The DSP is augmented by a large quantity of auxiliary RAM (ARAM) which may be used to store audio samples.The GCN audio hardware features a custom digital signal processor (DSP) which has the following characteristics:

81MHz instruction clock.
16-bit data words and addressing.
8KB (4Kword) Data RAM.
4KB (2Kword) Data ROM.
8KB (4Kword) Instruction RAM.
8KB (4Kword) Instruction ROM.
40-bit add-and-multiply-result registers.
Hardware ADPCM decoder.
Cached memory interface to ARAM.
DMA interface to main memory.
"Mailbox" registers for communicating with the CPU.

Register block Base	Size of Register block	common access size
`0xCC005000`	`0x200` bytes	16bit words

0xCC005000 2 r/w DSP Mailbox High (to DSP)

0xCC005002 2 r/w DSP Mailbox Low (to DSP)

bit31 of DSP Mailbox shows mail delivery status. (it will be cleared when the transfer is done)

to send mail just write data, high word first, with bit31 set.

0xCC005004 2 r CPU Mailbox High (from DSP)

0xCC005006 2 r CPU Mailbox Low (from DSP)

bit31 of CPU Mailbox shows mail delivery status.

0xCC00500a 2 ?/w AI DSP CSR - Control Status Register (DSP Status)

`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`

bit(s)

Description

Reset DSP (?)

DSP DMA Int Status

DSPINTMSK - DSP interrupt mask (*1)

DSPINT

read	0	no interrupts
	1	interrupt is active
write	0	no effect
	1	clear interrupt

ARINTMSK - ARAM interupt mask (*2)

ARINT -

read	0	no interrupts
	1	interrupt is active
write	0	no effect
	1	clear interupt

AIDINTMASK - AI interrupt mask (*3)

AIDINT

read	0	no interrupts
	1	interrupt is active
write	0	no effect
	1	clear interrupt

HALT - Halt DSP (?)

read	0
	1
write	0	unhalt DSP
	1	halt DSP (stop task execution)

PIINT - DSP Interrupt Assertion (?)

read	0
	1
write	0
	1	assert PI DSP interrupt

RES - Reset DSP (?)

read	0
	1
write	0
	1	reset DSP

(*1) disables only PI interrupt, doesnt effect assertion of DSPINT.
(*2) disables only PI interrupt, doesnt effect assertion of ARINT.
(*3) disables only PI interrupt, doesnt effect assertion of AIDINT.

0xCC005012 2 ?/? AR_SIZE

0xCC005016 2 ?/? AR_MODE

0xCC00501a 2 ?/? AR_REFRESH

0xCC005020 2 ?/? AR_DMA_MMADDR_H

0xCC005022 2 ?/? AR_DMA_MMADDR_L

0xCC005024 2 ?/? AR_DMA_ARADDR_H

0xCC005026 2 ?/? AR_DMA_ARADDR_L

0xCC005028 2 ?/? AR_DMA_CNT_H

bit(s)		description
15		type of transfer (0: write to aram 1: read from aram)
0-14		high bits of transfer length

0xCC00502a 2 ?/? AR_DMA_CNT_L

0xCC005030 2 ?/w DMA Start address (High)

Start of Audio Data

0xCC005032 2 ?/w DMA Start address (Low)

Start of Audio Data

0xCC005036 2 ?/w DMA Control/DMA length (Length of Audio Data)

`15`	`8`	`7`	`0`
`axxx`	`xxxx`	`xxxx`	`xxxx`

bit(s)		Description
	a	0=stop sample 1=play sample
	x	length/32 (max len is 0x000fffe0)

0xCC00503a 2 r/? DMA Bytes left

Counts down to zero showing how any bytes are left

index

5.6.1 internal DSP Registers

Registerblock Base	Size of Registerblock	common access size
`0xffc9`		`2`

0xFFC9 2 r/w DSCR - DSP dma Control Register

`15`	`8`	`7`	`0`

bit(s)

description

3-15

unused/reserved

DSP DMA busy

read	0
	1	Block length counter not yet zero, DMA is still busy
write	0	no effect ?
	1	no effect ?

DSP source/destination (DMA involved DSP memory)

0	DSP data memory
1	DSP instruction memory

transfer direction

0	from main memory to DSP memory
1	from DSP memory to main memory

0xFFCB 2 r/w DSBL - DSp dma Block Length

`15`	`8`	`7`	`0`

bit(s)		description
2-15		block length - This register is used to specify DSP DMA transfer length from bit 15 to bit 2
0-1		r: 2 bit of its LSBs - The transfer length is a multiple of 4 bytes

0xFFCD 2 r/w DSPA - DSp dma dsP memory Address High

`15`	`8`	`7`	`0`

bit(s)		description
1-15		DSP memory address - This register is used to specify DSP memory starting/current address from bit 15 to bit 1
0		r: 1 bit of its LSBs - The DSP memory address should be located at 2 word boundary

0xFFCE 2 r/w DSMAH - DSp dma Main memory Address High

`15`	`8`	`7`	`0`

bit(s)		description
10-15		r: 6 bits of its MSBs - This register is used to specify DSP DMA main memory starting/current address from bit 31 to bit 26, and always 0
0-9		main memory address high word - This register is used to specify DSP DMA main memory starting/current address from bit 25 to bit 16

0xFFCF 2 r/w DSMAL - DSp dma Main memory Address Low

`15`	`8`	`7`	`0`

bit(s)		description
2-15		main memory address - This register is used to specify DSP DMA main memory starting/current address from bit 15 to bit 2
0-1		r: 2 bits of its LSBs - The main memory address of this DMA should be located at 4 byte boundary

0xFFD4 2 r/w ACSAH - Accelerator aram Starting Address High

`15`	`8`	`7`	`0`

bit(s)		description
11-15		unused/reserved
0-10		wtarting address high-word - Bit 26 to bit 16 of ARAM starting address

0xFFD5 2 r/w ACSAL - Accelerator aram Starting Address Low

`15`	`8`	`7`	`0`

bit(s)		description
0-15		Starting address low-word - Bit 15 to bit 0 of ARAM starting address

0xFFD6 2 w ACEAH - Accelerator aram Ending Address High

`15`	`8`	`7`	`0`

bit(s)		description
15-11		unused/reserved
0-10		ending address high-word - Bit 26 to bit 16 of ARAM ending address

0xFFD7 2 w ACEAL - Accelerator aram Ending Address Low

`15`	`8`	`7`	`0`

bit(s)		description
0-15		ending address low-word - Bit 15 to bit 0 of ARAM ending address

0xFFD8 2 r/w ACCAH - Accelerator aram Current Address High

`15`	`8`	`7`	`0`

bit(s)

description

direction

0	accelerator read ARAM
1	accelerator write ARAM

11-14

unused/reserved

0-10

current address high-word - Bit 26 to bit 16 of ARAM current address

0xFFD9 2 r/w ACCAL - Accelerator aram Current Address Low

`15`	`8`	`7`	`0`

bit(s)		description
0-15		Bit 15 to Bit 0 of ARAM current address

0xFFEF 2 r/w AMDM - ARAM-Dma request Mask

`15`	`8`	`7`	`0`

bit(s)

description

1-15

unused/reserved

0	DMA request ARAM is unmasked
1	DMA request ARAM is masked

index

5.6.2 Operation

5.6.2.1 play raw audio sample

load DMA Start Address
setup DMA Control/DMA length

5.6.2.2 transfer from/to ARAM

set main memory address in AR_DMA_MMADDR_H and AR_DMA_MMADDR_L
set aram address in AR_DMA_ARADDR_H and AR_DMA_ARADDR_L
set length and transfer type in AR_DMA_CNT_H and AR_DMA_CNT_L
wait until bit 9 of AI DSP Control register gets cleared

5.6.2.3 reset DSP

set bit0 and bit11 of AI DSP Control Register

5.6.2.4 Boot DSP Task

send mail to DSP: 0x80F3A001, ram_mmem_addr
send mail to DSP: 0x80F3C002, ram_addr
send mail to DSP: 0x80F3A002, ram_length
send mail to DSP: 0x80F3B002, aram_mmem_addr (==0 ?)
send mail to DSP: 0x80F3D001, dsp_init_vector

index

5.7 DI - DVD Interface

Register block Base	Size of Register block	common access size
`0xCC006000`	`0x40`	`4`

0xCC006000 4 r/w DISR - DI Status Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`....`

bit(s)

description

7-31

reserved

BRKINT - Break Complete Interrupt Status (*1)

read	0	Interrupt has not been requested
	1	Interrupt has been requested
write	0	no effect
	1	clear Interrupt

BRKINTMASK - Break Complete Interrupt Mask. 0:masked, 1:enabled (*2)

TCINT - Transfer Complete Interrupt Status (*3)

read	0	Interrupt has not been requested
	1	Interrupt has been requested
write	0	no effect
	1	clear Interrupt

TCINTMASK - Transfer Complete Interrupt Mask. 0:masked, 1:enabled (*4)

DEINT - Device Error Interrupt Status (*5)

read	0	Interrupt has not been requested
	1	Interrupt has been requested
write	0	no effect
	1	clear Interrupt

DEINTMASK - Device Error Interrupt Mask. 0:masked, 1:enabled (*6)

BRK - DI Break (*7)

read	0	break not requested or break complete
	1	break requested and pending
write	0	no effect
	1	request break

(*1) On read this bit indicates the current status of the break complete interrupt. This interrupt is asserted when a Break cycle has completed (break acknowledge received from mass storage access device). When a `1` is written to this register, the interrupt is cleared.
(*2) Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of DISR[BRKINT]
(*3) On read this bit indicates the current status of the transfer complete interrupt. The Transfer Complete interrupt is asserted under the following conditions: a DMA mode transfer has completed (DMA finished) or an Immediate mode transfer has completed (transfer to/from DIIMMBUF has completed). When a `1` is written to this register, the interrupt is cleared. The assertion of TCIT is delayed until the DIDSTRBb (low) in order to guarantee the error interrupt occurs before transfer complete interrupt. If DIERRb is asserted during the current transaction, the transaction will be halted and TCINT will not be asserted.
(*4) Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of DISR[TCINT]
(*5) On read this bit indicates the current status of the mass storage access device error interrupt. To clear this interrupt, two actions must occur. When a `1` is written to this register, the internal interrupt is cleared. To reset the DIERRb signal, a command must be issued to the external DI device. If error occurs during the command packet, the drive has to delay the error assertion until the completion of the 12 bytes command transfer. In immediate mode, if error occurs during the data packet, the error assertion has to be delayed until the completion of the 4 bytes data transfer. In DMA mode, it has to be delayed until the completion of any 32 bytes data transfer.
(*6) Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of DISR[DEINT]
(*7) When a `1` is written to this bit, the DI controller interrupts the current command and sends a break signal to the mass storage access device. The break signal interrupts the current command on the mass storage access device. After the break sequence is complete (see TCINT), a new command may be sent to the mass storage access device. This bit is cleared after the break command is complete. Note that DI controller will delay the break signal assertion if it is in the middle of the command transfer. Hence break can only occur during the data transfer or when it is idle.

0xCC006004 4 r/w DICVR - DI Cover Register (status2)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`.smc`

bit(s)

Description

CVRINT - Cover Interrupt Status (*1)

read	0	cover interrupt has not been requested
	1	cover interrupt has been requested
write	0	no effect
	1	clear cover interrupt

CVRINTMASK - Cover Interrupt Mask. 0: masked, 1: enabled (*2)

CVR - State of the DICOVER signal. 0: cover closed, 1: cover opened

(*1) On read this bit indicates the current status of the Mass Storage Device Cover interrupt. When a `1` is written to this register, the internal interrupt is cleared. The Mass Storage Device Cover Interrupt is asserted when the status of the DICOVER signal changes (e.g., when the cover is opened or closed).
(*2) Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of DISR[CVRINT].

0xCC006008 4 r/w DICMDBUF0 - DI Command Buffer 0

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`cccc`	`cccc`	`1111`	`1111`	`2222`	`2222`	`2222`	`2222`

bit(s)		Description
24-31	c	command
16-23	1	subcommand 1
0-15	2	subcommand 2

0xCC00600c 4 r/w DICMDBUF1 - DI Command Buffer 1 (offset in 32 bit words)

0xCC006010 4 r/w DICMDBUF2 - DI Command Buffer 2 (source length)

0xCC006014 4 r/w DIMAR - DMA Memory Address Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`....`

bit(s)		description
26-31		reserved/unused
5-25		DIMAR - Address of source/destination buffer in main Memory
0-4		always zero (Address must be 32 byte aligned)

0xCC006018 4 r/w DILENGTH - DI DMA Transfer Length Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`....`

bit(s)		description
26-31		reserved/unused
5-25		DILENGTH - length of DMA data transfer in bytes (*1)
0-4		always zero (transfer length must be 32 byte aligned)

(*1) If a DMA command is interrupted by a break cycle, this register indicates the amount of data that was left to transfer before the DMA command was interrupted. If the length equals zero, it is a special case with command transfer only.

0xCC00601c 4 r/w DICR - DI Control Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`.mbe`

bit(s)		Description
`2`	m	RW - access mode, 0:read, 1:write
`1`	b	DMA - 0: immediate mode, 1: DMA mode (*1)
`0`	e	TSTART - transfer start. write 1: start transfer, read 1: transfer pending (*2)

(*1) The only mass storage device packet command which can use immediate mode is the `Register Access` command. When in immediate mode, the DIMAR and DILENGTH registers are ignored.

(*2) When read this bit represents the current command status. This bit is also cleared after the break completion and after DIERRb is asserted.

0xCC006020 4 r/w DIIMMBUF - DI immediate data buffer (error code ?)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`....`

bit(s)		description
24-31		REGVAL0 - data of register address+0
16-23		REGVAL1 - data of register address+1
8-15		REGVAL2 - data of register address+2
0-7		REGVAL3 - data of register address+3

0xCC006024 4 r DICFG - DI Configuration Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`....`

bit(s)		description
8-31		reserved/unused
0-7		CONFIG - during reset this register latches DIDD bus (only bit 0 used)

index

5.7.1 Drive Commands

DICMDBUF0	DICMDBUF1	DICMDBUF2	DIMAR	DILENGTH	DIIMMBUF	DICR	Description
`0x12000000`	`0x00000000`	`0x00000020`	ret: Drive-Info	`0x00000020`	-	DMA read	Inquiry
`0xa8000000`	Data-Position> >2	Data-Length	ret: Sector-Data	Data-Length	-	DMA read	read Sector
`0xa8000040`	`0x00000000`	`0x00000020`	ret: Disc-ID	`0x00000020`	-	DMA read	read Disc ID/Init Drive
`0xa8000080`	?	?	?	?	?	?	?
`0xa80000C0`	?	?	?	?	?	?	?
`0xab000000`	Position> >2	-	-	-	-	imm (read)	seek
`0xe0000000`	-	-	-	-	ret: Error-Code	imm read	request error Status
`0xe1??0000`	Stream-Position> >2	Stream-Length	-	-	-	imm read	play Audio Stream (?)
`0xe2??0000`	-	-	-	-	ret: Status (?)	imm read	request Audio Status
`0xe3000000`	-	-	-	-	-	imm (read)	stop Motor
`0xe4000000`	-	-	-	-	-	imm (read)	DVD Audio disable
`0xe4010000`	-	-	-	-	-	imm (read)	DVD Audio enable

index

5.7.2 Drive Debug Commands

DICMDBUF0	DICMDBUF1	DICMDBUF2	DIMAR	DILENGTH	DIIMMBUF	DICR	Description
`0xfe00????`	?	?	?	?	?	?	?
`0xfe010000`	offset	`0x00010000`	-	-	ret: 32bit value	imm (read)	read memory
`0xfe010100`	offset	`0x00010000`	-	-	32bit value	imm (write)	write memory
`0xfe018000`	offset	`0xff000000`	-	-	ret: 32bit value	imm (read)	read cache
`0xfe018100`	offset	`0xff000000`	-	-	32bit value	imm (write)	write cache
`0xfe100000`	?	?	-	-	-	imm (read)	?
`0xfe110000 (*)`	-	-	-	-	-	imm (read)	stop drive
`0xfe110100 (*)`	-	-	-	-	-	imm (read)	start drive
`0xfe114000 (*)`	-	-	-	-	-	imm (read)	accept copy
`0xfe118000 (*)`	-	-	-	-	-	imm (read)	do disc-check
`0xfe120000`	24bit address	`0x66756e63`	-	-	-	imm (read)	jsr to address '`func`'
`0xff004456`	`0x442d4741`	`0x4d450300`	-	-	-	imm (read)	unlock 2 '`DVD-GAME`'
`0xff014d41`	`0x54534849`	`0x5441024f`	-	-	-	imm (read)	unlock 1 '`MATSHITA`'

(*) commands can be ORed to perform several actions at once

index

5.7.3 Operation

5.7.3.1 Drive Info (Inquiry)

5.7.3.1.1 Structure of the Drive Info Data

start	end	size	Description
`0x0000`	`0x0001`	`0x02`	revision level
`0x0002`	`0x0003`	`0x02`	device code
`0x0004`	`0x0007`	`0x04`	release date
`0x0008`	`0x001F`	`0x18`	padding zeros

5.7.3.2 Read Disc ID / Init Disc

5.7.3.3 Read Sector

5.7.3.4 Seek

5.7.3.5 Request Error

5.7.3.5.1 Error Codes

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`aaaa`	`aaaa`	`nnnn`	`nnnn`	`nnnn`	`nnnn`	`nnnn`	`nnnn`

bit(s) description

`0x00`	ok
`0x01`	lid open
`0x02`	no disc/disc changed
`0x03`	no disc
`0x04`	motor off
`0x05`	disc not initialized/disc id not read

`0x000000`	ok
`0x020400`	Motor stopped
`0x020401`	Disk ID not read
`0x023A00`	Medium not present / Cover opened
`0x030200`	No Seek complete
`0x031100`	UnRecoverd read error
`0x040800`	Transfer protocol error
`0x052000`	Invalid command operation code
`0x052001`	Audio Buffer not set
`0x052100`	Logical block address out of range
`0x052400`	Invalid Field in command packet
`0x052401`	Invalid audio command
`0x052402`	Configuration out of permitted period
`0x056300`	End of user area encountered on this track
`0x062800`	Medium may have changed
`0x0B5A01`	Operator medium removal request

5.7.3.6 Play Audio Stream

5.7.3.7 Request Audio Status

5.7.3.8 Stop Motor

5.7.3.9 DVD Audio Disable

5.7.3.10 DVD Audio Enable

Command/Subcommand/Padding <- E4010000
Action <- 1
ACK (???)
Status2 <- Status2
INIT (???)
Status1 <- 2Ah
Status2 <- 0

5.7.3.11 Write Mem debug command

Note: This command is not really a single command but two commands in sequence. This command writes 'length' bytes to the specified address 'address' in the DVD drive addressable memory. 'length' is specified in bytes and must be in the range 1 to 12. If more data needs to be written, several commands need to be issued. 'address' is a 24 bit value, but a 32 bit value can be safely used. 'length' is a 16 bit value.

write the constant 0xfe010100 to DICMDBUF0 (0xCC006008)
write 'address' at DICMDBUF1 (0xCC00600C)
write 'length' to the upper 16 bits of DICMDBUF2 (0xCC006010) and clear the lower 16 bits.
start immediate read transfer: write 1 (TSTART) to DICR (0xCC00601C)
wait until transfer is complete, poll bit 0 (lowest order bit) of DICR (0xCC00601C), it will be cleared on end of transfer
write the data (up to 'length' bytes) to 0xCC00600C (write the first byte at 0xcc00600c, the second at 0xcc00600d, and so on)
start immediate read transfer: write 1 (TSTART) to DICR (0xCC00601C)
wait until transfer is complete, poll bit 0 (lowest order bit) of DICR (0xCC00601C), it will be cleared on end of transfer

index

5.7.4 DVD-ROM Subsystem

Matsushita MN103S13BGA Optical Disk Controller
Matsushita MN102H60GFA MicroComputer

5.7.4.1 Memory Map

start	end	size	description
`0x00008000`		4kb	internal (cpu) ram
`0x00080000`		128kb	firmware rom (*)
`0x00400000`			internal (controller) ram

(*) note: reading the firmware at its real location is prevented by the debug commands (imm buffer will not be changed at all). however you can read its contents from the memory mirrors, ie 0x000a0000-.

index

5.8 SI - Serial Interface

Register block Base	Size of Register block	common access size
`0xCC006400`	`0x100`	`4`

0xCC006400 4 r/w SIC0OUTBUF - SI Channel 0 Output Buffer (Joy-channel 1 Command)

0xCC00640c 4 r/w SIC1OUTBUF - SI Channel 1 Output Buffer (Joy-channel 2 Command)

0xCC006418 4 r/w SIC2OUTBUF - SI Channel 2 Output Buffer (Joy-channel 3 Command)

0xCC006424 4 r/w SIC3OUTBUF - SI Channel 3 Output Buffer (Joy-channel 4 Command)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24-31		unused/reserved
16-23		CMD - (*1)
8-15		OUTPUT0 - (*2)
0-7		OUTPUT1 - (*3)

This register is double buffered, so main processor writes to the SIC0OUTBUF will not interfere with the serial interface output transfer. Internally, a second buffer is used to hold the output data to be transferred across the serial interface. To check if SIC0OUTBUF has been transferred to the second buffer, main processor polls the SISR[WRST0] register. When SICOOUTBUF is transferred, SISR[WRST0] is cleared.

(*1) This byte is the opcode for the command sent to the controller during each command/response packet. This is the first data byte sent from the SI I/F to the game controller in the command/response packet.
(*2) This is the first data byte of the command packet. It is the second data byte sent from the SI I/F to the game controller in the command/response packet.
(*3) This is the second data byte of the command packet. It is the third data byte sent from the SI I/F to the game controller in the command/response packet.

0xCC006404 4 r Joy-channel 1 Buttons 1

0xCC006410 4 r SIC1INBUFH - SI Channel 1 Input Buffer High (Joy-channel 2 Buttons 1)

0xCC00641c 4 r Joy-channel 3 Buttons 1

0xCC006428 4 r Joy-channel 4 Buttons 1

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`...s`	`yxba`	`..LR`	`udrl`	`xxxx`	`xxxx`	`yyyy`	`yyyy`

bit(s)

Description

ERRSTAT - Error Status (*1)

0	no error on last transfer
1	error on last transfer

ERRLATCH - Error Latch (*2)

0	no error latched
1	error latched (check SISR)

24-29

bit 0-5 of input byte 0 (bit 6 and 7 are assumed to be 0)

16-23

input byte 1

8-15

input byte 2

0-7

input byte 3

(*1) This bit represents the current error status for the last SI polling transfer on this channel. This register is updated after each polling transfer on this channel.
(*2) This bit is an error status summary of the SISR error bits for this channel. If an error has occurred on a past SI transfer (polling or Com transfer), this bit will be set. To determine the exact error, read the SISR register. This bit is actually an `or` of the latched error status bits for this channel in the SISR. The bit is cleared by clearing the appropriate error status bits latched in the SISR. The no response error indicates that a controller is not present on thischannel.

0xCC006408 4 r/w Joy-channel 1 Buttons 2

0xCC006414 4 r/w Joy-channel 2 Buttons 2

0xCC006420 4 r/w Joy-channel 3 Buttons 2

0xCC00642c 4 r SIC3INBUFL - SI Channel 3 Input Buffer Low (Joy-channel 4 Buttons 2)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`xxxx`	`xxxx`	`yyyy`	`yyyy`	`llll`	`llll`	`rrrr`	`rrrr`

bit(s)		Description
24-31	x	input byte 4
16-23	y	input byte 5
8-15	l	input byte 6
0-7	r	input byte 7

SIC0INBUFH and SIC0INBUFL are double buffered to prevent inconsistent data reads due to main processor conflicting with incoming serial interface data. To insure data read from SIC0INBUFH and SIC0INFUBL are consistent, a locking mechanism prevents the double buffer from copying new data to these registers. Once SIC0INBUFH is read, both SIC0INBUFH and SIC0INBUFL are `locked` until SIC0INBUFL is read. While the buffers are `locked`, new data is not copied into the buffers. When SIC0INBUFL is read, the buffers become unlocked again.

0xCC006430 4 r/w SIPOLL - SI Poll Register (Joy-channel Control (?) (Calibration gun ?))

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`????`	`.???`	`....`	`..?.`	`eeee`	`....`

bit(s)

description

26-31

unused/reserved

16-25

X - 7 X lines register (*1)

8-15

Y - y times register (*2)

4-7

EN - controller port enable (1 bit per port, 1: enabled) (*3)

0-3

VBCPY - Vblank copy output channel (1 bit per port) (*4)

0	copy SICOUTBUF to output buffer after writing
1	copy SICOUTBUF to output buffer only on vblank

(*1) 7 X lines register: determines the number of horizontal video lines between polling (the polling interval). The polling begins at vsync. 7 is the minimum setting (determined by the time required to complete a single polling of the controller). The maximum setting depends on the current video mode (number of lines per vsync) and the SIPOLL[Y] register. This register takes affect after vsync.
(*2) This register determines the number of times the SI controllers are polled in a single frame. This register takes affect after vsync.
(*3) Enable polling of channel. When the channel is enabled, polling begins at the next vblank. When the channel is disabled, polling is stopped immediately after the current transaction. The status of this bit does not affect communication RAM transfers on this channel.
(*4) Normally main processor writes to the SIC0OUTBUF register are copied immediately to the channel 0 output buffer if a transfer is not currently in progress. When this bit is asserted, main processor writes to channel 0's SIC0OUTBUF will only be copied to the outbuffer on vblank. This is used to control the timing of commands to 3D LCD shutter glasses connected to the VI.

0xCC006434 4 r/w SICOMCSR - SI Communication Control Status Register (command)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`r?..`	`?ccs`	`.mmm`	`mmmm`	`.nnn`	`nnnn`	`eb..`	`...?`

bit(s)

description

TCINT - Transfer Complete Interrupt Status

read	0	transfer complete interrupt not requested
	1	transfer complete interrupt has been requested
write	0	no effect
	1	clear transfer complete interrupt

TCINTMSK - Transfer Complete Interrupt Mask (*1)

0	interrupt masked
1	interrupt enabled

COMERR - Communication Error

0	ok
1	error (see SiSr for the cause)

RDSTINT - Read Status Interrupt Status (*2)

read	0	Transfer Complete Interrupt not requested
	1	Transfer Complete Interrupt has been requested
write	0
	1

RDSTINTMSK - Read Status interrupt Mask (*3)

0	masked
1	enabled

25-26

Channel Number (?)

Channel Enable (?)

unused/reserved

16-22

OUTLNGTH - Communication Channel Output Length (*4)

unused/reserved

8-14

INLNGTH - Communication Channel Input Length (*4)

Command Enable (?)

callback enable

bit	Description
0	no callback
1	callback enabled

1-2

CHANNEL - (*5)

00	Channel 1
01	Channel 2
10	Channel 3
11	Channel 4

TSTART - Transfer Start (*6)

read	0	Command Complete
	1	Command Pending
write	0	Do not start command
	1	Start command

(*1) Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of SICOMCSR[TCINT]
(*2) On read this bit indicates the current status of the Read Status interrupt. The interrupt is set whenever SISR[RDSTn] bits are set. The interrupt is cleared when all of the RdSt bits in the SISR are cleared by reading from the Si Channel Input Buffers. This interrupt can be used to indicate that a polling transfer has completed and new data is captured in the input registers
(*3) Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of SICOMCSR[RDSTINT]
(*4) Minimum transfer is 1 byte. A value of 0 will transfer 128 bytes. These bits should not be modified while SICOM transfer is in progress.
(*5) These bits should not be modified while SICOM transfer is in progress.
(*6) When a `1` is written to this register, the current communication transfer is executed. The transfer begins immediately after the current transaction on this channel has completed. When read this bit represents the current transfer status. Once a communication transfer has been executed, polling will resume at the next vblank if the channel's SIPOLL[ENn] bit is set.

When programming the SICOMCSR after a SICOM transfers has already started (e.g., SICOMCSR[TSTART] is set), the software should read the current value first, then and/or in the proper data and then write the new data back. The software should not modify any of the transfer parameters (OUTLNGTH, INLNGTH, CHANNEL) until the current transfer is complete. This is done to prevent a SICOM transfer already in progress from being disturbed. When writing the data back, the software should not set the TSTART bit again unless the current transfer is complete and another transfer is required.

0xCC006438 4 r/w SISR - SI Status Register (channel select & status2)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`r???`	`aaaa`	`????`	`bbbb`	`????`	`cccc`	`????`	`dddd`

bit(s)

description

WR - Write SICnOUTBUF Register (*1)

read	0	buffer copied
	1	buffer not copied
write	0	no effect
	1	copy all buffers

reserved/unused

RDST0 - Read Status SIC0OINBUF Register (*2)

0	New data available, not read by main processor
1	No new data available, already read by main processor

WRST0 - Write Status SIC0OUTBUF Register (*3)

0	Buffer copied
1	Buffer not copied

NOREP0 - No Response Error Channel 0 (*4)

read	0	No Response Error not asserted
	1	No Response Error asserted
write	0	No effect
	1	Clear No Response Error

COLL0 - Collision Error Channel 0 (*5)

read	0	Collision Error not asserted
	1	Collision Error asserted
write	0	No effect
	1	Clear Collision Error

OVRUN0 - Over Run Error Channel 0 (*6)

read	0	Over Run Error not asserted
	1	Over Run Error asserted
write	0	No effect
	1	Clear Over Run Error

UNRUN - Under Run Error Channel 0 (*7)

read	0	Under Run not asserted
	1	Under Run asserted
write	0	No effect
	1	Clear Under Run Error

22-23

reserved/unused

16-21

Joy-channel 1 bits

14-15

reserved/unused

8-13

Joy-channel 2 bits

6-7

reserved/unused

0-5

Joy-channel 3 bits

(*1) Write SICnOUTBUF Register: This register controls and indicates whether the SICnOUTBUFs have been copied to the double buffered output buffers. This bit is cleared after the buffers have been copied.
(*2) This register indicates whether the SIC0INBUFs have been captured new data and whether the data has already been read by the main processor (read indicated by main processor read of SIC01NBUF[ERRSTAT, ERRLATCH, INPUT0, INPUT1)]
(*3) This register indicates whether the SIC0OUTBUFs have been copied to the double buffered output buffers. This bit is cleared after the buffers have been copied.
(*4) This register indicates that a previous transfer resulted in no response from the controller. This can also be used to detect whether a controller is connected. If no controller is connected, this bit will be set. Once set this bit remains set until it is cleared by the main processor. To clear this bit write `1` to this register.
(*5) This register indicates data collision between controller and main unit. Once set this bit remains set until it is cleared by the main processor. To clear this bit write `1` to this register.
(*6) This register indicates that the main unit has received more data than expected. Once set this bit remains set until it is cleared by the main processor. To clear this bit write `1' to this register.
(*7) This register indicates that the main unit has received less data than expected. Once set this bit remain set until it is cleared by the main processor. To clear this bit write `1` to this register.

0xcc00643c 4 R/W SIEXILK - SI EXI Clock Lock

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

LOCK - prevents CPU from setting EXI clock to 32MHz

0	32MHz EXI clock setting permitted
1	32MHz EXI clock setting not permitted

0-30

unused/reserved (always zero)

0xCC006480 0x80 r/w SI i/o buffer (access by word)

index

5.8.1 Operation

5.8.1.1 Serial Send Buffer

select channel: unset all bits in 0xcc006438 that are not corresponding to your channel and leave the others untouched.
Put output data into SI buffer (128 bytes maximum), word by word.
Send command: fill in 'c','m','n' and 'b' bits of 0xcc006434 accordingly, and set bits 's' and 'e'. leave other bits untouched.

5.8.1.2 Serial Get Result

simply read the SI buffer

index

5.9 EXI - External Interface

Upper memory (0xCC000000 and above) can't keep enough data for extra-large arrays, it's limited up to 0xFFFF bytes (suppose to be). EXI was designed to remove this limitation. EXI is used for access to big, unmapped areas of HW memory (such as bootrom or SRAM). This is the main task of EXI. Put another way, EXI can be used for providing access to slow, serial devices, such as memory cards. EXI is a complex of different devices, mapped to a single bus. The EXI bus is divided on 3 channels. Each channel has 3 unique devices. Each device is defined by its ID, and has its own address space.

EXI can be accessed in immediate mode, or via DMA channel. Each EXI device can generate up to 3 interrupts. They are called EXI, TC and EXT :


EXI	Device EXI Interrupt
TC	Transfer Completed (any mode)
EXT	Device Attached / Device Detached

Each EXI channel have its own register set, 5 32bit Registers each.

Register block Base	Size of Register block	common access size
`0xCC006800`	`0x40`	`4`

0xCC006800 4 EXI0CSR - EXI Channel 0 Parameter Register (Status?)

0xCC006814 4 EXI1CSR - EXI Channel 1 Parameter Register

0xCC006828 4 EXI2CSR - EXI Channel 2 Parameter Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s) Description

14-31 unused

13 ROMDIS - (EXI0 only) 1: rom de-scramble logic disabled (*1)

12 d EXT - Device Connected Bit (R) 1 if a device is connected on the specific channel

11 x EXTINT - External Insertion Interrupt Status (R) : check to poll EXT interrupt (or to detect device detach) (*4)

read	0	External Insertion Interrupt has not been requested
	1	External Insertion Interrupt has been requested
write	0	No effect
	1	Clear External Insertion Interrupt

10 m EXTINTMASK - EXT Interrupt Mask (1 - enable, 0 - disable) (*5)

7-9 210 CS - devices selected on this channel, each bit selecting one device. (*)

4-6 f CLK - used frequency (0-5)

`000`	1MHz
`001`	2MHz
`010`	4MHz
`011`	8MHz
`100`	16MHz
`101`	32MHz
`110`	reserved
`111`	reserved

3 t TCINT - Transfer Complete Interrupt Status

read	0	Transfer Complete Interrupt has not been requested
	1	Transfer Complete Interrupt has been requested
write	0	No effect
	1	Clear Transfer Complete Interrupt

2 m TCINTMASK - Transfer complete interrupt mask (1 - enable, 0 - disable) (*2)

1 e EXTINT - Interrupt Status (*6)

read	0	EXI Interrupt has not been requested
	1	EXI Interrupt has been requested
write	0	No effect
	1	Clear EXI Interrupt

0 m EXTINTMASK - EXI interrupt mask (1 - enable, 0 - disable)

(*)Only one of these three bits can be set to signify which device number has been selected on a specific channel.

(*6) This bit indicates the current status of the EXI0 interrupt. The interrupt is cleared by accessing the expansion device and clearing the interrupt on the device itself and cleared locally when a `1` is written to this register. This interrupt input is edge triggered.
(*1) This bit disables access to the IPL Mask ROM attached to CS1. Once this bit is enabled, it can only be disabled again by global reset. The ROM de-scramble logic will become disabled and any reads to the memory mapped ROM area will return all 0.When de-scrambler is enabled all EXI0 data will be de-scrambled, so only the IPL ROM may be accessed through EXI0 until ROMDIS is set to `1'. (this is usually done by the Bootstrap, see Boot process details)
(*2) Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of TCINT
(*3) Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of EXIINT
(*5) Interrupt masking prevents the interrupt from being sent to the main processor, but does not affect the assertion of EXICPR[EXTINT]
(*4) This interrupt indicates than an external EXI device has been removed from channel 1. To check whether the device has been inserted or removed, check the EXICPR[EXT] bit. When this bit is set, the channel's expansion EXI interface outputs go to high.

0xCC006804 4 r/w EXI0MAR - EXI Channel 0 DMA Start Address

0xCC006818 4 r/w EXI1MAR - EXI Channel 1 DMA Start Address

0xCC00682c 4 r/w EXI2MAR - EXI Channel 2 DMA Start Address

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`..dd`	`dddd`	`dddd`	`dddd`	`dddd`	`ddd.`	`....`

Physical Startaddress for DMA transfer. Must be aligned to 32 byte boundary .

(*) The memory address is the destination address when EXICR[RW] is set to `read` and is the source address when set to `write`.

0xCC006808 4 r/w EXI0LENGTH - EXI Channel 0 DMA Transfer Length

0xCC00681c 4 EXI Channel 1 DMA Transfer Length

0xCC006830 4 EXI Channel 2 DMA Transfer Length

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`..dd`	`dddd`	`dddd`	`dddd`	`dddd`	`ddd.`	`....`

Size of DMA transfer data in bytes. bits 0-4 are always zero (which means the size is 32 byte aligned)

0xCC00680c 4 r/w EXI0CR - EXI Channel 0 Control Register

0xCC006820 4 r/w EXI1CR - EXI Channel 1 Control Register

0xCC006834 4 r/w EXI2CR - EXI Channel 2 Control Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`..ll`	`ttme`

bit(s) Description

6-31 . unused

4-5 l TLEN - (data length-1) for immediate mode

`00`	1 byte
`01`	2 bytes
`10`	3 bytes
`11`	4 bytes

2-3 t RW - transfer type

`00`	read
`01`	write
`10`	read and write, invalid for DMA
`11`	undefined

1 m DMA - transfer mode (0 - immediate, 1 - DMA)

0 e TSTART - set, to start transfer. will be cleared after transfer completed.

0xCC006810 4 r/w EXI0DATA - EXI Channel 0 Immediate Data

0xCC006824 4 r/w EXI1DATA - EXI Channel 1 Immediate Data

0xCC006838 4 r/w EXI2DATA - EXI Channel 2 Immediate Data

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`dddd`	`dddd`	`dddd`	`dddd`	`dddd`	`dddd`	`dddd`	`dddd`

Data for read / write immediate operations (up to 4 bytes long).

The EXICPR must be configured to assert one of the devices CS, before the read or write operation can be performed. The actual read/write operation is triggered by the EXI0CR[TSTART] register and EXI0CR[DMA] set to `0`. Data is sent with MSB (bit 31) first.

index

5.9.1 Operation

5.9.1.1 Initializing the EXI Bus

clear all EXIs status registers (set to 0)
eventually initialize interrupt callbacks.

If you want to use DMA with EXI, you need your own properly installed EXI interrupt handlers. There is no need in callbacks and interrupts, if you are using EXI in immediate mode (just mask all TCs, to prevent unhandled interrupts).

5.9.1.2 Selecting a Specific EXI Device on an EXI Channel

set selected device number and frequency ('210' and f fields in status register)
eventually enable any existing callbacks

5.9.1.3 Deselecting EXI Devices on an EXI Channel

deselect device (clear corresponding '210' field)
eventually disable any existing callbacks

5.9.1.4 Performing an IMM Operation on a EXI Device

5.9.1.4.1 IMM Read

setup EXI Control Register (bit4-5:data length-1, bit2: 0 for read, bit1: 0 for immediate, bit1: 1 to start transfer)
wait until transfer has been completed (until bit 0 in EXI Control Register has been cleared)
get data from EXI IMM Data Register (up to 4 bytes)

5.9.1.4.2 IMM Write

write data to EXI IMM Data Register (up to 4 bytes)
setup EXI Control Register (bit4-5:data length-1, bit2: 1 for write, bit1: 0 for immediate, bit1: 1 to start transfer)
wait until transfer has been completed (until bit 0 in EXI Control Register has been cleared)

5.9.1.5 Performing a DMA Operation on a EXI Device

5.9.1.5.1 DMA Read

setup DMA buffer address
setup DMA length
setup EXI Control Register (bit4-5:data length-1, bit2: 0 for read, bit1: 1 for DMA, bit1: 1 to start transfer)
wait until transfer has been completed (until bit 0 in EXI Control Register has been cleared)

5.9.1.5.2 DMA Write

setup DMA buffer address
setup DMA length
setup EXI Control Register (bit4-5:data length-1, bit2: 1 for write, bit1: 1 for DMA, bit1: 1 to start transfer)
wait until transfer has been completed (until bit 0 in EXI Control Register has been cleared)

5.9.1.6 Wait for EXI transfer completed

To detect the end of a transfer on a specific channel either setup a 'transfer completed' callback (only works with DMA transfer) or periodically check bit 0 of the EXI Control Register (until cleared).

index

5.10 AI - Audio Streaming Interface

Registerblock Base	Size of Registerblock	common access size
`0xcc006c00`	`0x20`	`4`

0xCC006C00 r/w 4 AICR - Audio Interface Control Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`....`

bit(s) Description

7-31 reserved/unused

6 DSP Sample Rate

0	48 kHz sample rate
1	32 kHz sample rate

5 SCRESET Sample Counter Reset: When a `1` is written to this bit the AISLRCNT register is reset to 0

4 AIINTVLD Audio Interface Interrupt Valid.

This bit controls whether AIINT is affected by the AIIT register matching AISLRCNT. Once set, AIINT will hold its last value.

0	Match affects AIINT
1	AIINT hold last value.

3 AIINT Audio Interface Interrupt Status and clear. (*3)

r	0	Audio Interface Interrupt has not been requested
	1	Audio Interface Interrupt has been requested.
w	0	No effect
	1	Clear Audio Interface interrupt

2 AIINTMSK Audio interface Interrupt Mask

0	interrupt masked
1	Interrupt enabled

1 AFR: Auxiliary Frequency Register (*1)

0	48 kHz sample rate
1	32 kHz sample rate

0 PSTAT: Playing Status

0	Stop or Pause streaming audio (AISLR clock disabled)
1	Play streaming audio (AISLR clock enabled)

(*3 ) On read this bit indicates the current status of the audio interface interrupt. When a `1` is written to this register, the interrupt is cleared. This interrupt indicates that the AIIT register matches the AISLRCNT. This bit asserts regardless of the setting of AICR[AIMSK].
(*1 ) Controls the sample rate of the streaming audio data. When set to 32 kHz sample rate, the SRC will convert the streaming audio data to 48 kHz. This bit should only be changed when Streaming Audio is stopped (AICR[PSTAT] set to 0).
(*0) This bit enables the AISLR clock which controls the playing/stopping of audio streaming. When this bit is 1 AISLRCNT register will increment for every stereo pair of samples output.

0xCC006C04 r/w 4 AIVR - Audio Interface Volume Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`rrrr`	`rrrr`	`llll`	`llll`

bit(s)		description
16-31		unused/reserved
8-15	r	AVRR - Volume Right Channel (0x00 is muted,0xff is max)
0-7	l	AVRL - Volume Right Channel (0x00 is muted,0xff is max)

0xCC006C08 r 4 AISCNT - Audio Interface Sample Counter

Audio interface Sample Counter: This register counts the number of AIS stereo samples that have been output. It is enabled by AICR[PSTAT]. It can be cleared by the AICR[SCRESET] register.

0xCC006C0C r/w 4 AIIT - Audio Interface Interrupt Timing

This register indicates the stereo sample count to issue an audio interface interrupt to the main processor. The interrupt is issued when the value of the AISLRCNT register matches the content of this register.

index

5.11 GX FIFO (Graphic display lists)

GP have mapped 32-byte FIFO buffer, at 0xCC008000, which is controlled by write gather pipe (WPAR). when FIFO is filled (or overloaded by 32-bytes), WPAR performs burst transaction of primitive data to GP command FIFO. WPAR API also keeps watching for wrapping it on 32-buffer. You can think, that data is always looped and flows like in circle.

Registerblock Base	Size of Registerblock	common access size
`0xcc008000`	`4`	`any`

To access FIFO, you should just write data of any size to 0xCC008000, WPAR will control circularity and gathering automatically. By "data of any size" are assumed command types, vertices, vertex attributes etc stuff. All commands and primitive data are sending through mapped GP FIFO. GP task is only to draw primitives in embedded frame buffer, and then send it to XFB, for VI rendering. All render rules are stored in VI. GP can only change some copy rules, using pixel engine setup.

GP primitives also can be drawn, using Display List. In that case, GP FIFO takes only "CALL_DL" command with pointer to list data, and then GP command FIFO sequentially parsing primitive data from the main memory. Primitives can contains both direct and indexed vertexes as well. In first case, vertex attributes are sent directly using GP FIFO, in the other case the CPU sends only the pointer to vertex attribute data which is located in main memory.

index

5.11.1 internal BP registers

Registerblock Base	Size of Registerblock	common access size
`0x00`	`0x100`	`4 (1+3)`

Register	Description
`0x00`	GEN_MODE
`0x01`	display copy filter
`0x02`	display copy filter
`0x03`	display copy filter
`0x04`	display copy filter
`0x05`	?
`0x06`	IND_MTXA0
`0x07`	IND_MTXB0
`0x08`	IND_MTXC0
`0x09`	IND_MTXA1
`0x0a`	IND_MTXB1
`0x0b`	IND_MTXC1
`0x0c`	IND_MTXA2
`0x0d`	IND_MTXB2
`0x0e`	IND_MTXC2
`0x0f`	IND_IMASK
`0x10`	IND_CMD0 - tev indirect 0
`0x11`	IND_CMD1 - tev indirect 1
`0x12`	IND_CMD2 - tev indirect 2
`0x13`	IND_CMD3 - tev indirect 3
`0x14`	IND_CMD4 - tev indirect 4
`0x15`	IND_CMD5 - tev indirect 5
`0x16`	IND_CMD6 - tev indirect 6
`0x17`	IND_CMD7 - tev indirect 7
`0x18`	IND_CMD8 - tev indirect 8
`0x19`	IND_CMD9 - tev indirect 9
`0x1a`	IND_CMDA - tev indirect 10
`0x1b`	IND_CMDB - tev indirect 11
`0x1c`	IND_CMDC - tev indirect 12
`0x1d`	IND_CMDD - tev indirect 13
`0x1e`	IND_CMDE - tev indirect 14
`0x1f`	IND_CMDF - tev indirect 15
`0x20`	scissor x0,y0 (0x20156156)
`0x21`	scissor x1,y1 (0x213d5335)
`0x22`	SU_LPSIZE - field mode .. line width - point width
`0x23`	SU Counter (?) (0x23000000)
`0x24`	RAS Counter (?) (0x24000000)
`0x25`	RAS1_SS0 - ind tex coord scale 0
`0x26`	RAS1_SS1 - ind tex coord scale 1
`0x27`	RAS1_IREF
`0x28`	RAS1_TREF0 - tev order 0
`0x29`	RAS1_TREF1 - tev order 1
`0x2a`	RAS1_TREF2 - tev order 2
`0x2b`	RAS1_TREF3 - tev order 3
`0x2c`	RAS1_TREF4 - tev order 4
`0x2d`	RAS1_TREF5 - tev order 5
`0x2e`	RAS1_TREF6 - tev order 6
`0x2f`	RAS1_TREF7 - tev order 7

Register	Description
`0x30`	SU_SSIZE0 - texture offset 0 (Texture Size X, Y ?)
`0x31`	SU_TSIZE0 -
`0x32`	SU_SSIZE1 - texture offset 1
`0x33`	SU_TSIZE1 -
`0x34`	SU_SSIZE2 - texture offset 2
`0x35`	SU_TSIZE2 -
`0x36`	SU_SSIZE3 - texture offset 3
`0x37`	SU_TSIZE3 -
`0x38`	SU_SSIZE4 - texture offset 4
`0x39`	SU_TSIZE4 -
`0x3a`	SU_SSIZE5 - texture offset 5
`0x3b`	SU_TSIZE5 -
`0x3c`	SU_SSIZE6 - texture offset 6
`0x3d`	SU_TSIZE6 -
`0x3e`	SU_SSIZE7 - texture offset 7
`0x3f`	SU_TSIZE7 -
`0x40`	PE_ZMODE set z mode
`0x41`	PE_CMODE0 dithering / blend mode/color_update/alpha_update/set_dither
`0x42`	PE_CMODE1 destination alpha
`0x43`	PE_CONTROL comp z location z_comp_loc(0x43000040)pixel_fmt(0x43000041)
`0x44`	field mask (0x44000003)
`0x45`	PE_DONE - draw done (end of list marker) ?
`0x46`	some clock ? (0x46000000 - (((162000000/500)/4224) - 0x0200))
`0x47`	PE_TOKEN token B (16 bit)
`0x48`	PE_TOKEN_INT token A (16 bit)
`0x49`	EFB source rectangle top left
`0x4a`	EFB source rectangle width, height-1
`0x4b`	XFB target address
`0x4c`	?
`0x4d`	stride ?
`0x4e`	DispCopyYScale
`0x4f`	PE copy clear AR - set clear alpha and red components
`0x50`	PE copy clear GB - green and blue
`0x51`	PE copy clear Z - 24-bit Z value
`0x52`	pe copy execute?
`0x53`	copy filter
`0x54`	copy filter
`0x55`	bounding box (0x550003ff)
`0x56`	bounding box (0x560003ff)
`0x57`	?
`0x58`	? (0x5800000f)
`0x59`	scissor-box offset (0x5902acab)
`0x5a`	?
`0x5b`	?
`0x5c`	?
`0x5d`	?
`0x5e`	?
`0x5f`	?

Register	Description
`0x60`	?
`0x61`	?
`0x62`	?
`0x63`	?
`0x64`	TX_LOADTLUT0
`0x65`	TX_LOADTLUT1
`0x66`	?
`0x67`	metric ? (0x67000000)
`0x68`	field mode
`0x69`	some clock ? (0x69000000 - ((((162000000/500)> >11)&0x00ffffff)) - 0x0400)
`0x6a`	?
`0x6b`	?
`0x6c`	?
`0x6d`	?
`0x6e`	?
`0x6f`	?
`0x70`	?
`0x71`	?
`0x72`	?
`0x73`	?
`0x74`	?
`0x75`	?
`0x76`	?
`0x77`	?
`0x78`	?
`0x79`	?
`0x7a`	?
`0x7b`	?
`0x7c`	?
`0x7d`	?
`0x7e`	?
`0x7f`	?
`0x80`	TX_SETMODE0_I0 - 0x90 for linear
`0x81`	TX_SETMODE0_I1
`0x82`	TX_SETMODE0_I2
`0x83`	TX_SETMODE0_I3
`0x84`	TX_SETMODE1_I0
`0x85`	TX_SETMODE1_I1
`0x86`	TX_SETMODE1_I2
`0x87`	TX_SETMODE1_I3
`0x88`	TX_SETIMAGE0_I0 - texture size ?
`0x89`	TX_SETIMAGE0_I1
`0x8a`	TX_SETIMAGE0_I2
`0x8b`	TX_SETIMAGE0_I3
`0x8c`	TX_SETIMAGE1_I0
`0x8d`	TX_SETIMAGE1_I1
`0x8e`	TX_SETIMAGE1_I2
`0x8f`	TX_SETIMAGE1_I3

Register	Description
`0x90`	TX_SETIMAGE2_I0
`0x91`	TX_SETIMAGE2_I1
`0x92`	TX_SETIMAGE2_I2
`0x93`	TX_SETIMAGE2_I3
`0x94`	TX_SETIMAGE3_I0 - Texture Pointer
`0x95`	TX_SETIMAGE3_I1
`0x96`	TX_SETIMAGE3_I2
`0x97`	TX_SETIMAGE3_I3
`0x98`	TX_LOADTLUT0
`0x99`	TX_LOADTLUT1
`0x9a`	TX_LOADTLUT2
`0x9b`	TX_LOADTLUT3
`0x9c`	?
`0x9d`	?
`0x9e`	?
`0x9f`	?
`0xa0`	TX_SETMODE0_I4
`0xa1`	TX_SETMODE0_I5
`0xa2`	TX_SETMODE0_I6
`0xa3`	TX_SETMODE0_I7
`0xa4`	TX_SETMODE1_I4
`0xa5`	TX_SETMODE1_I5
`0xa6`	TX_SETMODE1_I6
`0xa7`	TX_SETMODE1_I7
`0xa8`	TX_SETIMAGE0_I4
`0xa9`	TX_SETIMAGE0_I5
`0xaa`	TX_SETIMAGE0_I6
`0xab`	TX_SETIMAGE0_I7
`0xac`	TX_SETIMAGE1_I4
`0xad`	TX_SETIMAGE1_I5
`0xae`	TX_SETIMAGE1_I6
`0xaf`	TX_SETIMAGE1_I7
`0xb0`	TX_SETIMAGE2_I4
`0xb1`	TX_SETIMAGE2_I5
`0xb2`	TX_SETIMAGE2_I6
`0xb3`	TX_SETIMAGE2_I7
`0xb4`	TX_SETIMAGE3_I4
`0xb5`	TX_SETIMAGE3_I5
`0xb6`	TX_SETIMAGE3_I6
`0xb7`	TX_SETIMAGE3_I7
`0xb8`	TX_SETTLUT_I4
`0xb9`	TX_SETTLUT_I5
`0xba`	TX_SETTLUT_I6
`0xbb`	TX_SETTLUT_I7
`0xbc`	?
`0xbd`	?
`0xbe`	?
`0xbf`	?

Register	Description
`0xc0`	TEV_COLOR_ENV_0 - tev op 0
`0xc1`	TEV_ALPHA_ENV_0 - tev op 1
`0xc2`	TEV_COLOR_ENV_1 -
`0xc3`	TEV_ALPHA_ENV_1
`0xc4`	TEV_COLOR_ENV_2 -
`0xc5`	TEV_ALPHA_ENV_2
`0xc6`	TEV_COLOR_ENV_3 -
`0xc7`	TEV_ALPHA_ENV_3
`0xc8`	TEV_COLOR_ENV_4 -
`0xc9`	TEV_ALPHA_ENV_4
`0xca`	TEV_COLOR_ENV_5 -
`0xcb`	TEV_ALPHA_ENV_5
`0xcc`	TEV_COLOR_ENV_6 -
`0xcd`	TEV_ALPHA_ENV_6
`0xce`	TEV_COLOR_ENV_7 -
`0xcf`	TEV_ALPHA_ENV_7
`0xd0`	TEV_COLOR_ENV_8 -
`0xd1`	TEV_ALPHA_ENV_8
`0xd2`	TEV_COLOR_ENV_9 -
`0xd3`	TEV_ALPHA_ENV_9
`0xd4`	TEV_COLOR_ENV_A -
`0xd5`	TEV_ALPHA_ENV_A
`0xd6`	TEV_COLOR_ENV_B -
`0xd7`	TEV_ALPHA_ENV_B
`0xd8`	TEV_COLOR_ENV_C -
`0xd9`	TEV_ALPHA_ENV_C
`0xda`	TEV_COLOR_ENV_D -
`0xdb`	TEV_ALPHA_ENV_D
`0xdc`	TEV_COLOR_ENV_E -
`0xdd`	TEV_ALPHA_ENV_E
`0xde`	TEV_COLOR_ENV_F -
`0xdf`	TEV_ALPHA_ENV_F
`0xe0`	TEV_REGISTERL_0
`0xe1`	TEV_REGISTERH_0
`0xe2`	TEV_REGISTERL_1
`0xe3`	TEV_REGISTERH_1
`0xe4`	TEV_REGISTERL_2
`0xe5`	TEV_REGISTERH_2
`0xe6`	TEV_REGISTERL_3
`0xe7`	TEV_REGISTERH_3
`0xe8`	Fog Range (0xe8000156)
`0xe9`	?
`0xea`	?
`0xeb`	?
`0xec`	? (guessed: tev_range_adj_c)
`0xed`	? (guessed: tev_range_adj_k)
`0xee`	TEV_FOG_PARAM_0 (0xee03ce38)
`0xef`	TEV_FOG_PARAM_1 (0xef471c82)

Register	Description
`0xf0`	TEV_FOG_PARAM_2 (0xf0000002)
`0xf1`	TEV_FOG_PARAM_3 (0xf1000000)
`0xf2`	TEV_FOG_COLOR (0xf2000000)
`0xf3`	TEV_ALPHAFUNC - alpha compare (0xf33f0000)
`0xf4`	TEV_Z_ENV_0 - z texture 0
`0xf5`	TEV_Z_ENV_1 - z texture 1
`0xf6`	TEV_KSEL_0 - Tev Swap Mode Table 0 (0xf6018064)
`0xf7`	TEV_KSEL_1 - Tev Swap Mode Table 1 (0xf701806e)
`0xf8`	TEV_KSEL_2 - Tev Swap Mode Table 2 (0xf8018060)
`0xf9`	TEV_KSEL_3 - Tev Swap Mode Table 3 (0xf901806c)
`0xfa`	TEV_KSEL_4 - Tev Swap Mode Table 4 (0xfa018065)
`0xfb`	TEV_KSEL_5 - Tev Swap Mode Table 5 (0xfb01806d)
`0xfc`	TEV_KSEL_6 - Tev Swap Mode Table 6 (0xfc01806a)
`0xfd`	TEV_KSEL_7 - Tev Swap Mode Table 7 (0xfd01806e)
`0xfe`	SS_MASK - BP Mask Register
`0xff`	?

0x00 4 w GEN_MODE

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

ZFREEZE

NBMP - Number of Bumpmaps

14-15

REJECT_EN - Culling Mode

0	none
1	negative
2	positive
3	all

NTEV

MS_EN

NCOL - Number of Colors

NTEX - Number of Texture Coords

0x01 4 w display copy filter

0x02 4 w display copy filter

0x03 4 w display copy filter

0x04 4 w display copy filter

0x05 4 w ?

0x06 4 w IND_MTXA0

0x09 4 w IND_MTXA1

0x0c 4 w IND_MTXA2

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
22		S
11		MB
0		MA

0x07 4 w IND_MTXB0

0x0a 4 w IND_MTXB1

0x0d 4 w IND_MTXB2

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
22		S
11		MD
0		MC

0x08 4 w IND_MTXC0

0x0b 4 w IND_MTXC1

0x0e 4 w IND_MTXC2

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
22		S
11		MF
0		ME

0x0f 4 w IND_IMASK

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
0		IMASK

0x10 4 w IND_CMD0

0x11 4 w IND_CMD1

0x12 4 w IND_CMD2

0x13 4 w IND_CMD3

0x14 4 w IND_CMD4

0x15 4 w IND_CMD5

0x16 4 w IND_CMD6

0x17 4 w IND_CMD7

0x18 4 w IND_CMD8

0x19 4 w IND_CMD9

0x1a 4 w IND_CMDA

0x1b 4 w IND_CMDB

0x1c 4 w IND_CMDC

0x1d 4 w IND_CMDD

0x1e 4 w IND_CMDE

0x1f 4 w IND_CMDF

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

21-23

PAD0 - padding zeros

FB - addprev

LB - utclod

16-18

TW - Wrap T

0	ITW_OFF
1	ITW_256
2	ITW_128
3	ITW_64
4	ITW_32
5	ITW_16
6	ITW_0
7

13-15

SW - Wrap S

0	ITW_OFF
1	ITW_256
2	ITW_128
3	ITW_64
4	ITW_32
5	ITW_16
6	ITW_0
7

9-12

M - Matrix ID

0	ITM_OFF
1	ITM_0
2	ITM_1
3	ITM_2
5	ITM_S0
6	ITM_S1
7	ITM_S2
9	ITM_T0
10	ITM_T1
11	ITM_T2

7-8

BS - Alpha Selection

0	ITBA_OFF
1	ITBA_S
2	ITBA_T
3	ITBA_U

4-6

BIAS

0	ITB_NONE
1	ITB_S
2	ITB_T
3	ITB_ST
4	ITB_U
5	ITB_SU
6	ITB_TU
7	ITB_STU

2-3

FMT - Format

0	ITF_8
1	ITF_5
2	ITF_4
3	ITF_3

0-1

BT - Indirect Tex Stage ID (0-3)

0x20 4 w SU_SCIS0 - Scissorbox Top Left Corner

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
12		X0 - Scissorbox X0 offset + 342
0		Y0 - Scissorbox Y0 offset + 342

0x21 4 w SU_SCIS1 - Scissorbox Bottom Right Corner

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
12		X1 - Scissorbox X1 offset + 342
0		Y1 - Scissorbox Y1 offset + 342

0x22 4 w SU_LPSIZE

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

PAD0

LINEASPECT

PTOFF

0	to 0
1	to 16th
2	to 8th
3	to 4th
4	to half
5	to 1

LTOFF

0	to 0
1	to 16th
2	to 8th
3	to 4th
4	to half
5	to 1

PSIZE

LSIZE

0x23 4 w SU Counter ?

0x24 4 w RAS Counter ?

0x25 4 w RAS1_SS - ind tex coord scale 0

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
12		TS1 - Ind. Tex Stage 1
8		SS1 - Ind. Tex Stage 1
4		TS0 - Ind. Tex Stage 0
0		SS0 - Ind. Tex Stage 0

0x26 4 w RAS1_SS - ind tex coord scale 1

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
12		TS1 - Ind. Tex Stage 3
8		SS1 - Ind. Tex Stage 3
4		TS0 - Ind. Tex Stage 2
0		SS0 - Ind. Tex Stage 2

0x27 4 w RAS1_IREF

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
21		BC3 - Ind. Tex Stage 3 NTexCoord
18		BI3 - Ind. Tex Stage 3 NTexMap
15		BC2 - Ind. Tex Stage 2 NTexCoord
12		BI2 - Ind. Tex Stage 2 NTexMap
9		BC1 - Ind. Tex Stage 1 NTexCoord
6		BI1 - Ind. Tex Stage 1 NTexMap
3		BC0 - Ind. Tex Stage 0 NTexCoord
0		BI0 - Ind. Tex Stage 0 NTexMap

0x28 4 w RAS1_TREF0

0x29 4 w RAS1_TREF1

0x2a 4 w RAS1_TREF2

0x2b 4 w RAS1_TREF3

0x2c 4 w RAS1_TREF4

0x2d 4 w RAS1_TREF5

0x2e 4 w RAS1_TREF6

0x2f 4 w RAS1_TREF7

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

PAD1

19-21

CC1 - Ind. Tex Stage 1 Channel ID

0	Color0
1	Color1
2	Alpha0
3	Alpha1
4	Color0A0
5	Color1A1
6	ColorZero
7	Bump

TE1 - Ind. Tex Stage 1 TexMap enable

TC1 - Ind. Tex Stage 1 TexCoord

TI1 - Ind. Tex Stage 1 TexMap

PAD0

CC0 - Ind. Tex Stage 0 Color ID

TE0 - Ind. Tex Stage 0 TexMap enable

TC0 - Ind. Tex Stage 0 TexCoord

TI0 - Ind. Tex Stage 0 TexMap

0x30 4 w SU_SSIZE0

0x32 4 w SU_SSIZE1

0x34 4 w SU_SSIZE2

0x36 4 w SU_SSIZE3

0x38 4 w SU_SSIZE4

0x3a 4 w SU_SSIZE5

0x3c 4 w SU_SSIZE6

0x3e 4 w SU_SSIZE7

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
19		PF - texcoord offset for points enable
18		LF - texcoord offset for lines enable
17		WS - s-cylindrical texcoord wrapping enable
16		BS - s-range bias enable
0		SSIZE - s-scale value -1 (U16)

0x31 4 w SU_TSIZE0

0x33 4 w SU_TSIZE1

0x35 4 w SU_TSIZE2

0x37 4 w SU_TSIZE3

0x39 4 w SU_TSIZE4

0x3b 4 w SU_TSIZE5

0x3d 4 w SU_TSIZE6

0x3f 4 w SU_TSIZE7

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
17		WT - t-cylindrical texcoord wrapping enable
16		BT - t-range bias enable
0		TSIZE - t-scale value -1 (U16)

0x40 4 w PE_ZMODE

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

MASK - Update enable

FUNC - Z-Buffer Compare Function

0	NEVER
1	LESS
2	EQUAL
3	LEQUAL
4	GREATER
5	NEQUAL
6	GEQUAL
7	ALWAYS

ENABLE - Z-Buffer enable

0x41 4 w PE_CMODE0

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

LOGICOP

0	CLEAR
1	AND
2	REVAND
3	COPY
4	INVAND
5	NOOP
6	XOR
7	OR
8	NOR
9	EQUIV
10	INV
11	REVOR
12	INVCOPY
13	INVOR
14	NAND
15	SET

BLENDOP

SFACTOR

DFACTOR

ALPHA_MASK

COLOR_MASK

DITHER_ENABLE

LOGICOP_ENABLE

BLEND_ENABLE

0x42 4 w PE_CMODE1

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
8		CONSTANT_ALPHA_ENABLE
0		CONSTANT_ALPHA

0x43 4 w PE_CONTROL

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

7-23

unused ?

Z Comp Loc (1: before tex)

3-5

Z Format

0	linear
1	near
2	mid
3	far

0-2

Pixel Format

0	RGB8_ Z24
1	RGBA6_Z24
2	RGB565_Z16
3	Z24
4	Y8
5	U8
6	V8
7	YUV420

0x44 4 w field mask ?

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID

0x45 4 w PE_DONE - draw done

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
1		1=end of list
0		?

0x46 4 w ? (some clock?)

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
9		? (must be 1)
0		((162000000/500)/4224)

0x47 4 w PE_TOKEN

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
0		Token

0x48 4 w PE_TOKEN_INT

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
0

0x49 4 w EFB Address Top Left

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
10		Y coordinate
0		X coordinate

0x4a 4 w EFB Address Width, Height-1

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
10		Height-1
0		Width

0x4b 4 w XFB Address

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
0		physical XFB Address > > 5

0x4c 4 w ?

0x4d 4 w stride ?

0x4e 4 w DispCopyYScale

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`....`

bit(s)		Description
24		RID
0		YSCALE - ((u32)(256.0/YSCALEIN))&0x1ff

0x4f 4 w PE copy clear AR - set clear alpha and red components

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`....`

bit(s)		Description
24		RID
8		A
0		R

0x50 4 w PE copy clear GB - green and blue

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`....`

bit(s)		Description
24		RID
8		G
0		B

0x51 4 w PE copy clear Z - 24-bit Z value

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`....`

bit(s)		Description
24		RID
0-23		Z - 24bit Z-Value

0x52 4 w pe copy execute?

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`....`	`....`	`....`	`....`	`....`	`....`	`....`	`....`

bit(s)		Description
24		RID
14		execute ? (1: to XFB 0: to texture ?!)
12-13		Frame 2 Field Mode
11		clear (1: clear EFB)
10		1: (256-(u32)(256.0/YSCALEIN)) > 0
9		?
7-8		disp copy gamma
4		target (XFB) pixel format
1		clamp
0		clamp

0x53 4 w copy filter

0x54 4 w copy filter

0x55 4 w bounding box

0x56 4 w bounding box

0x57 4 w ?

0x58 4 w ?

0x59 4 w Scissorbox Offset

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
10		YO - ((Scissorbox Y offset + 342)> >1)
0		XO - ((Scissorbox X offset + 342)> >1)

note: regs 0x5a-0x63 are left out (all unknown)

0x64 4 w TX_LOADTLUT0

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24-		rid
21-		pad0
0-		tlut base

0x65 4 w TX_LOADTLUT1

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24-		rid
21-		pad0
10-		count
0		tmem offset

0x66 4 w

0x67 4 w metric ?

0x68 4 w field mode

0x69 4 w ?

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
10		? (must be 1)
0		((162000000/500)> >11)

note: regs 0x6a-0x7f are left out (all unknown)

0x80 4 w TX_SETMODE0_I0 - Texture lookup and filtering mode

0x81 4 w TX_SETMODE0_I1 - Texture lookup and filtering mode

0x82 4 w TX_SETMODE0_I2 - Texture lookup and filtering mode

0x83 4 w TX_SETMODE0_I3 - Texture lookup and filtering mode

0xa0 4 w TX_SETMODE0_I4 - Texture lookup and filtering mode

0xa1 4 w TX_SETMODE0_I5 - Texture lookup and filtering mode

0xa2 4 w TX_SETMODE0_I6 - Texture lookup and filtering mode

0xa3 4 w TX_SETMODE0_I7 - Texture lookup and filtering mode

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

LODCLAMP / BIASCLAMP

0	off
1	on

MAXANISO

0	1
1	2 (requires edge LOD)
2	4 (requires edge LOD)
3	unused/reserved

LODBIAS (s2.5)

DIAGLOAD

0	edge LOD
1	diagonal LOD

MIN FILTER

0	near
1	near mip near
2	near mip lin
3	unused/reserved
4	linear
5	lin mip near
6	lin mip lin
7	unused/reserved

MAG FILTER

0	near
1	linear

WRAP T

0	clamp
1	repeat (*)
2	mirror (*)
3	unused/reserved

WRAP S (same as WRAP T)

(*) requires the texture size to be a power of two. (wrapping is implemented by a logical AND (SIZE-1))

0x84 4 w TX_SETMODE1_I0 - LOD Info

0x85 4 w TX_SETMODE1_I1 - LOD Info

0x86 4 w TX_SETMODE1_I2 - LOD Info

0x87 4 w TX_SETMODE1_I3 - LOD Info

0xa4 4 w TX_SETMODE1_I4 - LOD Info

0xa5 4 w TX_SETMODE1_I5 - LOD Info

0xa6 4 w TX_SETMODE1_I6 - LOD Info

0xa7 4 w TX_SETMODE1_I7 - LOD Info

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
8		MAX LOD (U4.4)
0		MIN LOD (U4.4)

0x88 4 w SETIMAGE0_I0 - Texture width, height, format

0x89 4 w SETIMAGE0_I1 - Texture width, height, format

0x8a 4 w SETIMAGE0_I2 - Texture width, height, format

0x8b 4 w SETIMAGE0_I3 - Texture width, height, format

0xa8 4 w SETIMAGE0_I4 - Texture width, height, format

0xa9 4 w SETIMAGE0_I5 - Texture width, height, format

0xaa 4 w SETIMAGE0_I6 - Texture width, height, format

0xab 4 w SETIMAGE0_I7 - Texture width, height, format

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

24-

rid

20-

format

0	I4
1	I8
2	IA4
3	IA8
4	RGB565
5	RGB5A3
6	RGBA8
7	unused/reserved
8	C4
9	C8
10	C14X2
11	unused/reserved
12	unused/reserved
13	unused/reserved
14	CMP
15	unused/reserved

10-

height - 1

width - 1

0x8c 4 w TX_SETIMAGE1_I0 - even LOD address in TMEM

0x8d 4 w TX_SETIMAGE1_I1 - even LOD address in TMEM

0x8e 4 w TX_SETIMAGE1_I2 - even LOD address in TMEM

0x8f 4 w TX_SETIMAGE1_I3 - even LOD address in TMEM

0xac 4 w TX_SETIMAGE1_I4 - even LOD address in TMEM

0xad 4 w TX_SETIMAGE1_I5 - even LOD address in TMEM

0xae 4 w TX_SETIMAGE1_I6 - even LOD address in TMEM

0xaf 4 w TX_SETIMAGE1_I7 - even LOD address in TMEM

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

IMAGE_TYPE

0	cached
1	preloaded

CACHE_HEIGHT

0	unused/reserved
1	unused/reserved
2	unused/reserved
3	32kb
4	128kb
5	512kb
6	unused/reserved
7	unused/reserved

CACHE_WIDTH (must be equal to CACHE_HEIGHT)

TMEM_OFFSET (address in TMEM > > 5)

0x90 4 w TX_SETIMAGE2_I0 - odd LOD address in TMEM

0x91 4 w TX_SETIMAGE2_I1 - odd LOD address in TMEM

0x92 4 w TX_SETIMAGE2_I2 - odd LOD address in TMEM

0x93 4 w TX_SETIMAGE2_I3 - odd LOD address in TMEM

0xb0 4 w TX_SETIMAGE2_I4 - odd LOD address in TMEM

0xb1 4 w TX_SETIMAGE2_I5 - odd LOD address in TMEM

0xb2 4 w TX_SETIMAGE2_I6 - odd LOD address in TMEM

0xb3 4 w TX_SETIMAGE2_I7 - odd LOD address in TMEM

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

CACHE_HEIGHT

0	none (if odd LOD is unused)
1	unused/reserved
2	unused/reserved
3	32kb
4	128kb
5	512kb
6	unused/reserved
7	unused/reserved

CACHE_WIDTH (must be equal to CACHE_HEIGTH)

TMEM_OFFSET - (address in TMEM > > 5)

0x94 4 w TX_SETIMAGE3_I0 - Address of Texture in main memory

0x95 4 w TX_SETIMAGE3_I1 - Address of Texture in main memory

0x96 4 w TX_SETIMAGE3_I2 - Address of Texture in main memory

0x97 4 w TX_SETIMAGE3_I3 - Address of Texture in main memory

0xb4 4 w TX_SETIMAGE3_I4 - Address of Texture in main memory

0xb5 4 w TX_SETIMAGE3_I5 - Address of Texture in main memory

0xb6 4 w TX_SETIMAGE3_I6 - Address of Texture in main memory

0xb7 4 w TX_SETIMAGE3_I7 - Address of Texture in main memory

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
0		IMAGE_BASE (physical address > > 5)

0x98 4 w TX_SETTLUT_0

0x99 4 w TX_SETTLUT_1

0x9a 4 w TX_SETTLUT_2

0x9b 4 w TX_SETTLUT_3

0xb8 4 w TX_SETTLUT_4

0xb9 4 w TX_SETTLUT_5

0xba 4 w TX_SETTLUT_6

0xbb 4 w TX_SETTLUT_7

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

FORMAT

0	IA8
1	RGB565
2	RGB5A3
3	reserved/unused

TMEM_OFFSET (offset of TLUT from start of TMEM high bank >
5)

0x9c 4 w ?

0x9d 4 w ?

0x9e 4 w ?

0x9f 4 w ?

0xbc 4 w ?

0xbd 4 w ?

0xbe 4 w ?

0xbf 4 w ?

0xc0 4 w TEV_COLOR_ENV_0

0xc2 4 w TEV_COLOR_ENV_1

0xc4 4 w TEV_COLOR_ENV_2

0xc6 4 w TEV_COLOR_ENV_3

0xc8 4 w TEV_COLOR_ENV_4

0xca 4 w TEV_COLOR_ENV_5

0xcc 4 w TEV_COLOR_ENV_6

0xce 4 w TEV_COLOR_ENV_7

0xd0 4 w TEV_COLOR_ENV_8

0xd2 4 w TEV_COLOR_ENV_9

0xd4 4 w TEV_COLOR_ENV_A

0xd6 4 w TEV_COLOR_ENV_B

0xd8 4 w TEV_COLOR_ENV_C

0xda 4 w TEV_COLOR_ENV_D

0xdc 4 w TEV_COLOR_ENV_E

0xde 4 w TEV_COLOR_ENV_F

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
22		DEST
20		SHIFT
19		CLAMP
18		SUB
16		BIAS
12		SELA
8		SELB
4		SELC
0		SELD

SELA - SELD Format:

`0x0`	CC_CPREV
`0x1`	CC_APREV
`0x2`	CC_C0
`0x3`	CC_A0
`0x4`	CC_C1
`0x5`	CC_A1
`0x6`	CC_C2
`0x7`	CC_A2
`0x8`	CC_TEXC
`0x9`	CC_TEXA
`0xA`	CC_RASC
`0xB`	CC_RASA
`0xC`	CC_ONE
`0xD`	CC_HALF
`0xE`	CC_KONST
`0xF`	CC_ZERO

0xc1 4 w TEV_ALPHA_ENV_0

0xc3 4 w TEV_ALPHA_ENV_1

0xc5 4 w TEV_ALPHA_ENV_2

0xc7 4 w TEV_ALPHA_ENV_3

0xc9 4 w TEV_ALPHA_ENV_4

0xcb 4 w TEV_ALPHA_ENV_5

0xcd 4 w TEV_ALPHA_ENV_6

0xcf 4 w TEV_ALPHA_ENV_7

0xd1 4 w TEV_ALPHA_ENV_8

0xd3 4 w TEV_ALPHA_ENV_9

0xd5 4 w TEV_ALPHA_ENV_A

0xd7 4 w TEV_ALPHA_ENV_B

0xd9 4 w TEV_ALPHA_ENV_C

0xdb 4 w TEV_ALPHA_ENV_D

0xdd 4 w TEV_ALPHA_ENV_E

0xdf 4 w TEV_ALPHA_ENV_F

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
22		DEST
20		SHIFT
19		CLAMP
18		SUB
16		BIAS
13		SELA
10		SELB
7		SELC
4		SELD
2		TSWAP
0		RSWAP

SELA - SELD Format:

0	CA_APREV
1	CA_A0
2	CA_A1
3	CA_A2
4	CA_TEXA
5	CA_RASA
6	CA_KONST
7	CA_ZERO

0xe0 4 w TEV_REGISTERL_0

0xe2 4 w TEV_REGISTERL_1

0xe4 4 w TEV_REGISTERL_2

0xe6 4 w TEV_REGISTERL_3

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

TYPE

0	Color (?)
1	Constant (?)

0xe1 4 w TEV_REGISTERH_0

0xe3 4 w TEV_REGISTERH_1

0xe5 4 w TEV_REGISTERH_2

0xe7 4 w TEV_REGISTERH_3

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

TYPE

0	Color (?)
1	Constant (?)

0x88 4 w Fog Range

0x89 4 w

0x8A 4 w

0x8B 4 w

0xec (guessed) 4 w tev_range_adj_c

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

CENTER - Screen X Center for range Adjustment

ENB - Range-Adjustment enable

0	TEV_ENB_DISABLE
1	TEV_ENB_ENABLE

0xed (guessed) 4 w tev_range_adj_k

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
0-11		r2k (u4.8) - specifies the range adjustment function

range adjustment = sqr((x*x)+(k*k))/k

0xee 4 w TEV_FOG_PARAM_0 - "a" parameter of the screen to eye space conversion function

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
19		A_SIGN_SHIFT
11		A_EXPN
0		A_MANT (signed 11e8)

0xef 4 w TEV_FOG_PARAM_1 - the "b" parameter of the z screen to eye space conversion function

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
0		B_MAG (unsigned 0.24)

0xf0 4 w TEV_FOG_PARAM_2 - amount to pre-shift screen z

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
0-4		B_SHF - equivalent to the value of "b" parameter's exponent + 1

The Z-Screen to Eyespace conversion is defined as:

Ze = A / (B_MAG - (Zs > > B_SHF))

0xf1 4 w TEV_FOG_PARAM_3 - fog type

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

21-23

FSEL

0	FSEL_OFF; No fog
1	reserved
2	FSEL_LIN; linear Fog
3	reserved
4	FSEL_EXP; Exponential Fog
5	FSEL_EX2; Exponential Squared Fog
6	FSEL_BXP; Backward Exp Fog
7	FSEL_BX2 Backward Exp Squared Fog

PROJ

0	PERSP; Perspective projection
1	ORTHO; Orthographic projection

C_SIGN (*)

C_EXPN (*)

0-10

C_MANT (*)

(*) Specifies the amount to subtract from eye-space Z after range adjustment.

0xf2 4 w TEV_FOG_COLOR - Value of Fog Color

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
16		R
8		G
0		B

0xf3 4 w TEV_ALPHAFUNC

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

LOGIC

0	AND
1	OR
2	XOR
3	XNOR

OP1

OP0

0xf4 4 w TEV_Z_ENV_0

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID -
0-23		ZOFF/BIAS -

0xf5 4 w TEV_Z_ENV_1

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

RID

2-3

0	disable
1	add
2	replace
3	unused/reserved

0-1

TYPE/FORMAT

0	u8
1	u16
2	u24
3	unused/reserved

0xf6 4 w TEV_KSEL_0

0xf7 4 w TEV_KSEL_1

0xf8 4 w TEV_KSEL_2

0xf9 4 w TEV_KSEL_3

0xfa 4 w TEV_KSEL_4

0xfb 4 w TEV_KSEL_5

0xfc 4 w TEV_KSEL_6

0xfd 4 w TEV_KSEL_7

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		RID
19		KASEL1
14		KCSEL1
9		KASEL0
4		KCSEL0
2		XGA
0		XRB

KCSEL - tev const color sel

0	1
1	7_8
2	3_4
3	5_8
4	1_2
5	3_8
6	1_4
7	1_8
8
9
10
11
12	K0
13	K1
14	K2
15	K3
16	K0_R
17	K1_R
18	K2_R
19	K3_R
20	K0_G
21	K1_G
22	K2_G
23	K3_G
24	K0_B
25	K1_B
26	K2_B
27	K3_B
28	K0_A
29	K1_A
30	K2_A
31	K3_A

KASEL - tev const alpha sel

0	1
1	7_8
2	3_4
3	5_8
4	1_2
5	3_8
6	1_4
7	1_8
8
9
10
11
12
13
14
15
16	K0_R
17	K1_R
18	K2_R
19	K3_R
20	K0_G
21	K1_G
22	K2_G
23	K3_G
24	K0_B
25	K1_B
26	K2_B
27	K3_B
28	K0_A
29	K1_A
30	K2_A
31	K3_A

0xfe 4 w SS_MASK - BP Mask Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`****`	`****`

bit(s)		description
24	*	RID
0-23		MASK (*)

(*) This Register can be used to limit to which bits of BP registers is actually written to. the mask is only valid for the next BP command, and will reset itself.

0xff 4 w ?

index

5.11.2 internal CP Registers

Registerblock Base	Size of Registerblock	common access size
`0x20`	`0xa0`	`4`

Register		description
`0x20`		?
`0x30`		MATINDEX_A - Texture Matrix Index 0-3
`0x40`		MATINDEX_B - Texture Matrix Index 4-7
`0x50`		VCD_LO - Vertex Descriptor (VCD) low, format 0
`0x51`		VCD_LO - Vertex Descriptor (VCD) low, format 1
`0x52`		VCD_LO - Vertex Descriptor (VCD) low, format 2
`0x53`		VCD_LO - Vertex Descriptor (VCD) low, format 3
`0x54`		VCD_LO - Vertex Descriptor (VCD) low, format 4
`0x55`		VCD_LO - Vertex Descriptor (VCD) low, format 5
`0x56`		VCD_LO - Vertex Descriptor (VCD) low, format 6
`0x57`		VCD_LO - Vertex Descriptor (VCD) low, format 7
`0x60`		VCD_HI - Vertex Descriptor (VCD) high, format 0
`0x61`		VCD_HI - Vertex Descriptor (VCD) high, format 1
`0x62`		VCD_HI - Vertex Descriptor (VCD) high, format 2
`0x63`		VCD_HI - Vertex Descriptor (VCD) high, format 3
`0x64`		VCD_HI - Vertex Descriptor (VCD) high, format 4
`0x65`		VCD_HI - Vertex Descriptor (VCD) high, format 5
`0x66`		VCD_HI - Vertex Descriptor (VCD) high, format 6
`0x67`		VCD_HI - Vertex Descriptor (VCD) high, format 7
`0x70`		VAT_A - Vertex Attribute Table (VAT) group 0, format 0
`0x71`		VAT_A - Vertex Attribute Table (VAT) group 0, format 1
`0x72`		VAT_A - Vertex Attribute Table (VAT) group 0, format 2
`0x73`		VAT_A - Vertex Attribute Table (VAT) group 0, format 3
`0x74`		VAT_A - Vertex Attribute Table (VAT) group 0, format 4
`0x75`		VAT_A - Vertex Attribute Table (VAT) group 0, format 5
`0x76`		VAT_A - Vertex Attribute Table (VAT) group 0, format 6
`0x77`		VAT_A - Vertex Attribute Table (VAT) group 0, format 7
`0x80`		VAT_B - Vertex Attribute Table (VAT) group 1, format 0
`0x81`		VAT_B - Vertex Attribute Table (VAT) group 1, format 1
`0x82`		VAT_B - Vertex Attribute Table (VAT) group 1, format 2
`0x83`		VAT_B - Vertex Attribute Table (VAT) group 1, format 3
`0x84`		VAT_B - Vertex Attribute Table (VAT) group 1, format 4
`0x85`		VAT_B - Vertex Attribute Table (VAT) group 1, format 5
`0x86`		VAT_B - Vertex Attribute Table (VAT) group 1, format 6
`0x87`		VAT_B - Vertex Attribute Table (VAT) group 1, format 7
`0x90`		VAT_C - Vertex Attribute Table (VAT) group 2, format 0
`0x91`		VAT_C - Vertex Attribute Table (VAT) group 2, format 1
`0x92`		VAT_C - Vertex Attribute Table (VAT) group 2, format 2
`0x93`		VAT_C - Vertex Attribute Table (VAT) group 2, format 3
`0x94`		VAT_C - Vertex Attribute Table (VAT) group 2, format 4
`0x95`		VAT_C - Vertex Attribute Table (VAT) group 2, format 5
`0x96`		VAT_C - Vertex Attribute Table (VAT) group 2, format 6
`0x97`		VAT_C - Vertex Attribute Table (VAT) group 2, format 7

Register		description
`0xA0`		ARRAY_BASE - vertices ptr
`0xa1`		ARRAY_BASE - normals ptr
`0xa2`		ARRAY_BASE - color 0 ptr
`0xa3`		ARRAY_BASE - color 1 ptr
`0xa4`		ARRAY_BASE - texture 0 coordinate ptr
`0xa5`		ARRAY_BASE - texture 1 coordinate ptr
`0xa6`		ARRAY_BASE - texture 2 coordinate ptr
`0xa7`		ARRAY_BASE - texture 3 coordinate ptr
`0xa8`		ARRAY_BASE - texture 4 coordinate ptr
`0xa9`		ARRAY_BASE - texture 5 coordinate ptr
`0xaa`		ARRAY_BASE - texture 6 coordinate ptr
`0xab`		ARRAY_BASE - texture 7 coordinate ptr
`0xac`		ARRAY_BASE - IndexRegA - general purpose array 0 ptr
`0xad`		ARRAY_BASE - IndexRegB - general purpose array 1 ptr
`0xae`		ARRAY_BASE - IndexRegC - general purpose array 2 ptr
`0xaf`		ARRAY_BASE - IndexRegD - general purpose array 3 ptr
`0xB0`		ARRAY_STRIDE - size of vertices
`0xb1`		ARRAY_STRIDE - size of normals
`0xb2`		ARRAY_STRIDE - size of colors 0
`0xb3`		ARRAY_STRIDE - size of colors 1
`0xb4`		ARRAY_STRIDE - size of texture 0 coordinates
`0xb5`		ARRAY_STRIDE - size of texture 1 coordinates
`0xb6`		ARRAY_STRIDE - size of texture 2 coordinates
`0xb7`		ARRAY_STRIDE - size of texture 3 coordinates
`0xb8`		ARRAY_STRIDE - size of texture 4 coordinates
`0xb9`		ARRAY_STRIDE - size of texture 5 coordinates
`0xba`		ARRAY_STRIDE - size of texture 6 coordinates
`0xbb`		ARRAY_STRIDE - size of texture 7 coordinates
`0xbc`		ARRAY_STRIDE - IndexRegA - general purpose array 0 stride
`0xbd`		ARRAY_STRIDE - IndexRegB - general purpose array 1 stride
`0xbe`		ARRAY_STRIDE - IndexRegC - general purpose array 2 stride
`0xbf`		ARRAY_STRIDE - IndexRegD - general purpose array 3 stride

0x20 4 w ?

0x30 4 w MATIDX_REG_A

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		`TEX3IDX - Index for Texture 3 matrix`
18		`TEX2IDX - Index for Texture 2 matrix`
12		`TEX1IDX - Index for Texture 1 matrix`
6		`TEX0IDX - Index for Texture 0 matrix`
0		`POSIDX - Index for Position/Normal matrix`

0x40 4 w MATIDX_REG_B

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
18		`TEX7IDX - Index for Texture 7 matrix`
12		`TEX6IDX - Index for Texture 6 matrix`
6		`TEX5IDX - Index for Texture 5 matrix`
0		`TEX4IDX - Index for Texture 4 matrix`

0x50 4 R/W VCD_LO - Vertex Descriptor low Format 0

0x51 4 R/W VCD_LO - Vertex Descriptor low Format 1

0x52 4 R/W VCD_LO - Vertex Descriptor low Format 2

0x53 4 R/W VCD_LO - Vertex Descriptor low Format 3

0x54 4 R/W VCD_LO - Vertex Descriptor low Format 4

0x55 4 R/W VCD_LO - Vertex Descriptor low Format 5

0x56 4 R/W VCD_LO - Vertex Descriptor low Format 6

0x57 4 R/W VCD_LO - Vertex Descriptor low Format 7

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
17-31		unused
15-16		`COL1 - Color1 (Specular)`
13-14		`COL0 - Color0 (Diffused)`
11-12		`NRM - Normal or Normal/Binormal/Tangent`
9-10		`POS - Position`
8		`T7MIDX`
7		`T6MIDX`
6		`T5MIDX`
5		`T4MIDX`
4		`T3MIDX`
3		`T2MIDX`
2		`T1MIDX`
1		`T0MIDX - Texture Coordinate 0 Matrix Index`
0		`PMIDX - Position/Normal Matrix Index (*1)`

(*1) position and normal matrices are stored in 2 seperate areas of internal XF memory, but there is a one to one correspondence between normal and position index.If index 'A' is used for the position, then index 'A' needs to be used for the normal as well.

0x60 4 R/W VCD_HI - Vertex Descriptor high Format 0

0x61 4 R/W VCD_HI - Vertex Descriptor high Format 1

0x62 4 R/W VCD_HI - Vertex Descriptor high Format 2

0x63 4 R/W VCD_HI - Vertex Descriptor high Format 3

0x64 4 R/W VCD_HI - Vertex Descriptor high Format 4

0x65 4 R/W VCD_HI - Vertex Descriptor high Format 5

0x66 4 R/W VCD_HI - Vertex Descriptor high Format 6

0x67 4 R/W VCD_HI - Vertex Descriptor high Format 7

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
							`..tt`

bit(s)		description
16-		unused
14-15		`TEX7` - texture coordinate 7
12-13		`TEX6` - texture coordinate 6
10-11		`TEX5` - texture coordinate 5
8-9		`TEX4` - texture coordinate 4
6-7		`TEX3` - texture coordinate 3
4-5		`TEX2` - texture coordinate 2
2-3		`TEX1` - texture coordinate 1
0-1	t	`TEX0` - texture coordinate 0

vertex descriptor data

value	Vertex/Color	Pos/Tex Matrix Index
0	no data present	no data present
1	direct	direct
2	i8 - indirect/8 bit index	n/a
3	i16 - indirect/16 bit index	n/a

0x70 4 w CP_VAT_REG_A - Format 0

0x71 4 w CP_VAT_REG_A - Format 1

0x72 4 w CP_VAT_REG_A - Format 2

0x73 4 w CP_VAT_REG_A - Format 3

0x74 4 w CP_VAT_REG_A - Format 4

0x75 4 w CP_VAT_REG_A - Format 5

0x76 4 w CP_VAT_REG_A - Format 6

0x77 4 w CP_VAT_REG_A - Format 7

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s) description

31 NORMALINDEX3 (*1)

0	single index per normal
1	triple-index per nine-normal

30 BYTEDEQUANT (should always be 1)

0	shift does not apply to u8/s8 components
1	shift applies to u8/s8 components

25 TEX0SHFT

22 TEX0FMT

21 TEX0CNT

18 COL1FMT (Specular)

17 COL1CNT (Specular)

14 COL0FMT (Diffused)

13 COL0CNT (Diffused)

10 NRMFMT

9 NRMCNT

4 POSSHFT

1 POSFMT

0 POSCNT

(*1) when nine-normals are selected in indirect mode, input will be treated as three staggered indices (one per triple biased by components size), into normal table (note: first index internally biased by 0, second by 1, third by 2)

0x80 4 w CP_VAT_REG_B - Format 0

0x81 4 w CP_VAT_REG_B - Format 1

0x82 4 w CP_VAT_REG_B - Format 2

0x83 4 w CP_VAT_REG_B - Format 3

0x84 4 w CP_VAT_REG_B - Format 4

0x85 4 w CP_VAT_REG_B - Format 5

0x86 4 w CP_VAT_REG_B - Format 6

0x87 4 w CP_VAT_REG_B - Format 7

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
31		`VCACHE_ENHANCE (must always be 1)`
28		`TEX4FMT`
27		`TEX4CNT`
22		`TEX3SHFT`
19		`TEX3FMT`
18		`TEX3CNT`
13		`TEX2SHFT`
10		`TEX2FMT`
9		`TEX2CNT`
4		`TEX1SHFT`
1		`TEX1FMT`
0		`TEX1CNT`

0x90 4 w CP_VAT_REG_C - Format 0

0x91 4 w CP_VAT_REG_C - Format 1

0x92 4 w CP_VAT_REG_C - Format 2

0x93 4 w CP_VAT_REG_C - Format 3

0x94 4 w CP_VAT_REG_C - Format 4

0x95 4 w CP_VAT_REG_C - Format 5

0x96 4 w CP_VAT_REG_C - Format 6

0x97 4 w CP_VAT_REG_C - Format 7

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
27		`TEX7SHFT`
24		`TEX7FMT`
23		`TEX7CNT`
18		`TEX6SHFT`
15		`TEX6FMT`
14		`TEX6CNT`
9		`TEX5SHFT`
6		`TEX5FMT`
5		`TEX5CNT`
0		`TEX4SHFT`

Vertex Attribute Data Formats

CompCount

value	coords	normals	tex coords	colors
0	two (x,y)	three	one (s)	three (r,g,b)
1	three (x,y,z)	nine	two (s,t)	four (r,g,b,a)

CompSize

value	coords	normals	colors
0	u8	n/a	16 bit rgb565
1	s8	s8	24 bit rgb888
2	u16	n/a	32 bit rgb888x
3	s16	s16	16 bit rgba4444
4	f32	f32	24 bit rgba6666
5	n/a	n/a	32 bit rgba8888
6	unused	unused	unused
7	unused	unused	unused

Shift

coords	normals	colors
location of decimal point	n/a (byte: 6, short: 14)	n/a

This shift applies to all s16/u16 components, and all s8/s8 components when ByteDequant is asserted.

0xA0 4 w ARRAY_BASE

0xA1 4 w ARRAY_BASE

0xA2 4 w ARRAY_BASE

0xA3 4 w ARRAY_BASE

0xA4 4 w ARRAY_BASE

0xA5 4 w ARRAY_BASE

0xA6 4 w ARRAY_BASE

0xA7 4 w ARRAY_BASE

0xA8 4 w ARRAY_BASE

0xA9 4 w ARRAY_BASE

0xAA 4 w ARRAY_BASE

0xAB 4 w ARRAY_BASE

0xAC 4 w ARRAY_BASE

0xAD 4 w ARRAY_BASE

0xAE 4 w ARRAY_BASE

0xAF 4 w ARRAY_BASE

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
26-		unused
0-25		array base addres in main memory

0xB0 4 w ARRAY_STRIDE

0xB1 4 w ARRAY_STRIDE

0xB2 4 w ARRAY_STRIDE

0xB3 4 w ARRAY_STRIDE

0xB4 4 w ARRAY_STRIDE

0xB5 4 w ARRAY_STRIDE

0xB6 4 w ARRAY_STRIDE

0xB7 4 w ARRAY_STRIDE

0xB8 4 w ARRAY_STRIDE

0xB9 4 w ARRAY_STRIDE

0xBa 4 w ARRAY_STRIDE

0xBb 4 w ARRAY_STRIDE

0xBc 4 w ARRAY_STRIDE

0xBd 4 w ARRAY_STRIDE

0xBe 4 w ARRAY_STRIDE

0xBf 4 w ARRAY_STRIDE

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
8-		unused
0-7		array stride

index

5.11.3 internal XF Memory

Every register in the transform unit is mapped to a unique 32b address. All addresses are available to the xform register load command (command 0x30).

The first block is formed by the matrix memory. Its address range is 0 to 1 k, but only 256 entries are used. This memory is organized in a 64 entry by four 32b words. Each word has a unique address and is a single precision floating point number. For block writes, the addresses auto increment. The memory is implemented in less than 4-32b rams, then it is possible that the memory writes to this block will require a minimum write size larger than 1 word.

start	end	size	description
`0x0000`		`32`	Matrix Ram word 0
`0x0001`	`0x00ff`		Matrix Ram word (n)
`0x0100`	`0x03ff`	`0x300`	not used

0 - position matrix (4*3)
0xF0 - (texture?) transform matrix (4*3)

The second block of memory is the normal matrix memory. It is organized as 32 rows of 3 words. Each word has a unique address and is a single precision floating point number. Also, each word written is 32b, but only the 20 most significant bits are kept. For simplicity, the minimum granularity of writes will be 3 words:

start	end	size	description
`0x0400`	`0x0402`	`20`	Normal Ram words 0,1,2
`0x0403`	`0x045f`		Normal Ram word (n)
`0x0460`	`0x05ff`		not used

0x400 - normal transform matrix (3*3)

The third block of memory holds the dual texture transform matrices. The format is identical to the first block of matrix memory. There are also 64 rows of 4 words for these matrices. These matrices can only be used for the dual transform of regular textures:

start	end	size	description
`0x0500`		`32`	Matrix Ram word 0
`0x0501`	`0x05ff`		Matrix Ram word (n)

0x5F4 - dual texture transform matrix (4*3)

The fourth block of memory is the light memory. This holds all the lighting information (light vectors, light parameters, etc.). Both global state and ambient state are stored in this memory. Each word written is 32b, but only the 20 most significant bits are kept. Each row is 3 words wide. Minimum word write size is 3 words.

start	end	size	description
`0x0600`			reserved
`0x0601`			reserved
`0x0602`			reserved
`0x0603`		`32 bit`	Light0 - RGBA
`0x0604`		`20 bit`	Light0A0 - cos atten. A-0
`0x0605`		`20 bit`	Light0A1 - cos atten. A-1
`0x0606`		`20 bit`	Light0A2 - cos atten. A-2
`0x0607`		`20 bit`	Light0K0 - dist atten. A-0
`0x0608`		`20 bit`	Light0K1 - dist atten. A-1
`0x0609`		`20 bit`	Light0K2 - dist atten. A-2
`0x060a`		`20 bit`	Light0Lpx - x light pos, or inf ldir x
`0x060b`		`20 bit`	Light0Lpy - y light pos, or inf ldir y
`0x060c`		`20 bit`	Light0Lpz - z light pos, or inf ldir z
`0x060d`		`20 bit`	Light0Dx/Hx - light dir x, or 1/2 angle x
`0x060e`		`20 bit`	Light0Dy/Hy - light dir y, or 1/2 angle y
`0x060f`		`20 bit`	Light0Dz/Hz - light dir z, or 1/2 angle z
`0x0610`	`0x067f`		Light(n)data - see Light0 data
`0x0680`	`0x07ff`		not used

index

5.11.4 internal XF Registers

Registerblock Base	Size of Registerblock	common access size
`0x1000`	`0x54`	`4`

Register		description
`0x1000`		Error (=0x3f)
`0x1001`		Diagnostics
`0x1002`		State0 - Internal State Register 0
`0x1003`		State1 - Internal State Register 1
`0x1004`		Xf_clock - Enables Power Saving Mode
`0x1005`		ClipDisable - clip mode (=0)
`0x1006`		Perf0 - Performance monitor selects (=0)
`0x1007`		Perf1 - Xform target performance register
`0x1008`		InVertexSpec - INVTXSPEC - (=0x01)
`0x1009`		NumColors - NUMCOLORS - (=0x00)
`0x100a`		Ambient0 - chan Ambient color 0 (=0x00)
`0x100b`		Ambient1- chan Ambient color 1 (=0x00)
`0x100c`		Material0 - chan Material ID 0 (=0xffffffff)
`0x100d`		Material1 - chan Material ID 1 (=0xffffffff)
`0x100e`		COLOR0CNTRL (=0x0401)
`0x100f`		COLOR1CNTRL (=0x0401)
`0x1010`		ALPHA0CNTRL (=0x0401)
`0x1011`		ALPHA1CNTRL (=0x0401)
`0x1012`		DualTexTrans - (=0x01)
`0x1013`		?
`0x1014`		?
`0x1015`		?
`0x1016`		?
`0x1017`		?
`0x1018`		MatrixIndex0 - MATINDEX A
`0x1019`		MatrixIndex1 - MATINDEX B
`0x101a`		ScaleX - Viewport Scale X
`0x101b`		ScaleY - Viewport Scale Y
`0x101c`		Scale Z - Viewport Scale Z
`0x101d`		OffsetX - Viewport Offset X
`0x101e`		OffsetY - Viewport Offset Y
`0x101f`		OffsetZ - Viewport Offset Z
`0x1020`		ProjectionA - A parameter in projection equations
`0x1021`		ProjectionB - B parameter in projection equations
`0x1022`		ProjectionC - C parameter in projection equations
`0x1023`		ProjectionD - D parameter in projection equations
`0x1024`		ProjectionE - E parameter in projection equations
`0x1025`		ProjectionF - F parameter in projection equations
`0x1026`		ProjectOrtho

Register		description
`0x103f`		NUMTEX - Number of active Textures
`0x1040`		TEX0
`0x1041`		TEX1
`0x1042`		TEX2
`0x1043`		TEX3
`0x1044`		TEX4
`0x1045`		TEX5
`0x1046`		TEX6
`0x1047`		TEX7

Register		description
`0x1050`		DUALTEX0
`0x1051`		DUALTEX1
`0x1052`		DUALTEX2
`0x1053`		DUALTEX3
`0x1054`		DUALTEX4
`0x1055`		DUALTEX5
`0x1056`		DUALTEX6
`0x1057`		DUALTEX7

0x1000 4 w Error

0x1001 4 w Diagnostics

0x1002 4 w State 0 - Internal State Register 0

0x1003 4 w State 1 - Internal State Register 1

0x1004 4 w Xf_clock

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

0	no power saving when idle
1	enable Power saving when idle

0x1005 4 w ClipDisable

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
2		when set, disable cpoly clipping acceleration (default==0)
1		when set, disable trivial rejection (default==0)
0		when set, disable clipping detection (default==0)

0x1006 4 w Perf0 - Performance monitor selects

0x1007 4 w Perf1 - Xform target performance Register

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
0-6		Xform internal target performance (Cycles per Vertex)

0x1008 4 w INVTXSPEC

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s) description

4-7 HOST_TEXTURES - number of host supplied texture coordinates

0	no host supplied textures
1	1 host supplied texture pair (S0, T0)
2-8	2-8 host supplied texturepairs
9-15	reserved/unused

2-3 HOST_NORMAL - host supplied normal

0	no host supplied normal
1	host supplied normal
2	host supplied normal and binormals

0-1 HOST_COLORS - host supplied color0 usage

0	no host supplied color information
1	host supplied color 0
2	host supplied color 0 and color 1

0x1009 4 w NUMCOLORS

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

value		description
0		`No colors`
1		`One color -` Xform supplies 1 color (host supplied or computed)
2		`Two colors -` Xform supplies 2 colors (host supplied or computed)

Selects the number of output colors

0x100a 4 w XF_AMBIENT0 - Ambient color 0 specifications

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		`RED`
16		`GREEN`
8		`BLUE`
0		`ALPHA`

0x100b 4 w XF_AMBIENT1 - Ambient color 1 specifications

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		`RED`
16		`GREEN`
8		`BLUE`
0		`ALPHA`

0x100c 4 w XF_MATERIAL0 - global color0 material specification

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		`RED`
16		`GREEN`
8		`BLUE`
0		`ALPHA`

0x100d 4 w XF_MATERIAL1 - global color1 material specification

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24		`RED`
16		`GREEN`
8		`BLUE`
0		`ALPHA`

0x100e 4 w COLOR0CNTRL

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s) description

14 LIGHT7 - Light 7 is source

0	Do not use Light
1	Use light

13 LIGHT6 - Light6 is source

0	Do not use Light
1	Use light

12 LIGHT5 - Light5 is source

0	Do not use Light
1	Use light

11 LIGHT4 - Light4 is source

0	Do not use Light
1	Use light

10 ATTENSELECT - Attenuation Select function

0	Select specular (N.H) attenuation
1	Select diffuse spotlight (L.Ldir) attenuation

9 ATTENENABLE - Attenuation Enable function

0	Select 1.0
1	Select Attenuation fraction

7-8 DIFFUSEATTEN - Diffuse Attenuation function

00	Select 1.0
01	Select N.L, signed
10	Select N.L clamped to [0,1.0]
11

6 AMBIENT_SRC - Ambient source

0	Use register Ambient0 register
1	Use CP supplied vertex color 0

5 LIGHT3 - Light3 is source

0	Do not use light
1	Use light

4 LIGHT2 - Light2 is source

0	Do not use light
1	Use light

3 LIGHT1 - Light1 is source

0	Do not use light
1	Use light

2 LIGHT0 - Light0 is source

0	Do not use light
1	Use light

1 LIGHTFUNC - Color0 Light Function

0	Use 1.0
1	Use Illum0

0 MATERIAL_SRC - Color0 Material source

0	Use register (Material 0)
1	Use CP supplied Vertex color 0

0x100f 4 w COLOR1CNTRL

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s) description

14 LIGHT7 - Light 7 is source

0	Do not use Light
1	Use light

13 LIGHT6 - Light6 is source

0	Do not use Light
1	Use light

12 LIGHT5 - Light5 is source

0	Do not use Light
1	Use light

11 LIGHT4 - Light4 is source

0	Do not use Light
1	Use light

10 ATTENSELECT - Attenuation Select function

0	Select specular (N.H) attenuation
1	Select diffuse spotlight (L.Ldir) attenuation

9 ATTENENABLE - Attenuation Enable function

0	Select 1.0
1	Select Attenuation fraction

7-8 DIFFUSEATTEN - Diffuse Attenuation function

00	Select 1.0
01	Select N.L, signed
10	Select N.L clamped to [0,1.0]
11

6 AMBIENT_SRC - Ambient source

0	Use register Ambient1 register
1	Use CP supplied vertex color 1

5 LIGHT3 - Light3 is source

0	Do not use light
1	Use light

4 LIGHT2 - Light2 is source

0	Do not use light
1	Use light

3 LIGHT1 - Light1 is source

0	Do not use light
1	Use light

2 LIGHT0 - Light0 is source

0	Do not use light
1	Use light

1 LIGHTFUNC - Color1 Light Function

0	Use 1.0
1	Use Illum1

0 MATERIAL_SRC - Color1 Material source

0	Use register (Material 1)
1	Use CP supplied Vertex color 1

0x1010 4 w ALPHA0CNTRL

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s) description

14 LIGHT7 - Light 7 alpha is source

0	Do not use Light
1	Use light

13 LIGHT6 - Light6 alpha is source

0	Do not use Light
1	Use light

12 LIGHT5 - Light5 alpha is source

0	Do not use Light
1	Use light

11 LIGHT4 - Light4 alpha is source

0	Do not use Light
1	Use light

10 ATTENSELECT - Attenuation Select function

0	Select specular (N.H) attenuation
1	Select diffuse spotlight (L.Ldir) attenuation

9 ATTENENABLE - Attenuation Enable function

0	Select 1.0
1	Select Attenuation fraction

7-8 DIFFUSEATTEN - Diffuse Attenuation function

00	Select 1.0
01	Select N.L, signed
10	Select N.L clamped to [0,1.0]
11

6 AMBIENT_SRC - Ambient source

0	Use register Ambient0 alpha register
1	Use CP supplied vertex color 0 alpha

5 LIGHT3 - Light3 alpha is source

0	Do not use light
1	Use light

4 LIGHT2 - Light2 alpha is source

0	Do not use light
1	Use light

3 LIGHT1 - Light1 alpha is source

0	Do not use light
1	Use light

2 LIGHT0 - Light0 alpha is source

0	Do not use light
1	Use light

1 LIGHTFUNC - Color0 alpha Light Function

0	Use 1.0
1	Use Illum0

0 MATERIAL_SRC - Color0 alpha Material source

0	Use register (Material 0 alpha)
1	Use CP supplied Vertex color 0 alpha

0x1011 4 w ALPHA1CNTRL

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s) description

14 LIGHT7 - Light 7 alpha is source

0	Do not use Light
1	Use light

13 LIGHT6 - Light6 alpha is source

0	Do not use Light
1	Use light

12 LIGHT5 - Light5 alpha is source

0	Do not use Light
1	Use light

11 LIGHT4 - Light4 alpha is source

0	Do not use Light
1	Use light

10 ATTENSELECT - Attenuation Select function

0	Select specular (N.H) attenuation
1	Select diffuse spotlight (L.Ldir) attenuation

9 ATTENENABLE - Attenuation Enable function

0	Select 1.0
1	Select Attenuation fraction

7-8 DIFFUSEATTEN - Diffuse Attenuation function

00	Select 1.0
01	Select N.L, signed
10	Select N.L clamped to [0,2.0]
11

6 AMBIENT_SRC - Ambient source

0	Use register Ambient1 alpha register
1	Use CP supplied vertex color 1 alpha

5 LIGHT3 - Light3 alpha is source

0	Do not use light
1	Use light

4 LIGHT2 - Light2 alpha is source

0	Do not use light
1	Use light

3 LIGHT1 - Light1 alpha is source

0	Do not use light
1	Use light

2 LIGHT0 - Light0 alpha is source

0	Do not use light
1	Use light

1 LIGHTFUNC - Color0 alpha Light Function

0	Use 1.0
1	Use Illum0

0 MATERIAL_SRC - Color0 alpha Material source

0	Use register (Material 0 alpha)
1	Use CP supplied Vertex color 0 alpha

0x1012 4 w DualTexTrans

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

0	disable dual texture transform feature
1	enable dual transform for all texture coordinates

0x1013 4 w ?

0x1014 4 w ?

0x1015 4 w ?

0x1016 4 w ?

0x1017 4 w ?

0x1018 4 w MatrixIndex0

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
24-29		Tex3 matrix index
23-18		Tex2 matrix index
12-17		Tex1 matrix index
6-11		Tex0 matrix index
0-5		Geometry matrix index

0x1019 4 w MatrixIndex1

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
18-23		Tex7 matrix index
12-17		Tex6 matrix index
6-11		Tex5 matrix index
0-5		Tex4 matrix index

0x101A 4 w Viewport

0x101B 4 w Viewport

0x101C 4 w Viewport

0x101D 4 w Viewport

0x101E 4 w Viewport

0x101F 4 w Viewport

Viewport Matrix

		description
`0x101A`	f32	wd / 2
`0x101B`	f32	-ht / 2
`0x101C`	f32	ZMAX * (farZ - nearZ)
`0x101D`	f32	xOrig + wd / 2 + 342
`0x101E`	f32	yOrig + ht / 2 + 342
`0x101F`	f32	ZMAX * farZ

ZMAX is 16777215.0 (maximum 24-bit Z buffer value, or 'infinite')

0x1020 4 w Projection Matrix

0x1021 4 w Projection Matrix

0x1022 4 w Projection Matrix

0x1023 4 w Projection Matrix

0x1024 4 w Projection Matrix

0x1025 4 w Projection Matrix

Projection Matrix

		orthogonal	perspective
`0x1020`	f32	2.0 / (r - l)	(1.0f / tanf(fovy * 0.5F)) / aspect
`0x1021`	f32	-(r+l) / (r-l)	0
`0x1022`	f32	2.0 / (t-b)	(1.0f / tanf(fovy * 0.5F))
`0x1023`	f32	-(t+b)/(t-b)	0
`0x1024`	f32	-1.0/(f-n)	-n * 1.0f / (f-n)
`0x1025`	f32	-(f)/(f-n)	-(fn) 1.0f / (f-n)

0x1026 4 w ProjectOrtho

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)

description

If set selects orthographic otherwise non-orthographic (Zh or 1.0 select)

note: regs 0x1027-0x103e skipped (all unknown)

0x103f 4 w NUMTEX - Number of active Textures

0x1040 4 w TEX0

0x1041 4 w TEX1

0x1042 4 w TEX2

0x1043 4 w TEX3

0x1044 4 w TEX4

0x1045 4 w TEX5

0x1046 4 w TEX6

0x1047 4 w TEX7

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s) description

15-17 EMBOSS_LIGHT - Bump mapping source light (*1)

12-14 EMBOSS_SOURCE - bump mapping source texture (*2)

7-11 SOURCE_ROW - regular texture source row (*3)

0	GEOM_INROW -
1	NORMAL_INROW -
2	COLORS_INROW -
3	BINORMAL_T_INROW -
4	BINORMAL_B_INROW -
5	TEX0_INROW -
6	TEX1_INROW -
7	TEX2_INROW -
8	TEX3_INROW -
9	TEX4_INROW -
a	TEX5_INROW -
b	TEX6_INROW -
c	TEX7_INROW -
d
e
f

4-6 TEXGEN_TYPE

0	REGULAR - Regular transformation (transform incoming data)
1	EMBOSS_MAP - texgen bump mapping
2	COLOR_STRGBC0 - Color texgen: (s,t)=(r,g:b) (g and b are concatenated), color 0
3	COLOR_STRGBC1 - Color texgen: (s,t)=(r,g:b) (g and b are concatenated), color 1

3 reserved/unused

2 INPUT_FORM - format of source input data for regular textures

0	AB11 - (A, B, 1.0, 1.0) (used for regular texture source)
1	ABC1 - (A, B, C, 1.0) (used for geometry or normal source)

1 PROJECTION

0	ST - (s,t): texmul is 2x4
1	STQ - (s,t,q): texmul is 3x4

0 reseved/unused

(*1) n: use light #n for bump map direction source (10 to 17)
(*2) n: use regular transformed tex(n) for bump mapping source
(*3) Specifies location of incoming textures in vertex (row specific) (i.e.: geometry is row0, normal is row1, etc . . . ) for regular transformations

note: regs 0x1048-104f skipped (all unknown)

0x1050 4 w DUALTEX0

0x1051 4 w DUALTEX1

0x1052 4 w DUALTEX2

0x1053 4 w DUALTEX3

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`

bit(s)		description
8		`NORMAL_ENABLE` - specifies if texture coordinate should be normalized before send transform.
6-7		unused
0-5		`DUALMTX` - base row of the dual transform matrix for regular texture coordinate0 (63 max, simelar to 0x1018/0x1019)

index

5.11.5 GP packet description

The first thing in a GP Packet is the command type (8 bit).Next follows actual primitive data. It may vary on each opcode type.

5.11.5.1 Command Type

`7`	`0`
`oooo`	`ovvv`

bit(s)		description
	o	Opcode
	v	Vertex Attribute Table Index (VAT)

5.11.5.1.1 opcodes

opcode	Description
`0x00`	NOP - No Operation
`0x08`	Load CP REG
`0x10`	Load XF REG
`0x20`	Load INDX A
`0x28`	Load INDX B
`0x30`	Load INDX C
`0x38`	Load INDX D
`0x40`	CALL DL - Call Displaylist
`0x48`	Invalidate Vertex Cache
`0x61`	Load BP REG (SU_ByPassCmd)
`0x80`	QUADS - Draw Quads (*)
`0x90`	TRIANGLES - Draw Triangles (*)
`0x98`	TRIANGLESTRIP - Draw Triangle Strip (*)
`0xA0`	TRIANGLEFAN - Draw Triangle Fan (*)
`0xA8`	LINES - Draw Lines (*)
`0xB0`	LINESTRIP - Draw Line Strip (*)
`0xB8`	POINTS - Draw Points (*)

(*) all draw opcodes must be Or-ed with used VAT index (0...7)

5.11.5.2 Drawing Commands

8 bits	16 bits	n
opcode	number of vertices	vertex data

Vertex data may be in one of many formats. The VCD tells wether data for a component exists (and if yes, if it is direct or indexed) and the VAT tells the actual format of the respective component. Each individual component may or may not exist, but the order is fixed as follows:

PNMTXIDX - Position/Normal Matrix Index
TEX0MTXIDX - Texture 0 Matrix Index
TEX1MTXIDX - Texture 1 Matrix Index
TEX2MTXIDX - Texture 2 Matrix Index
TEX3MTXIDX - Texture 3 Matrix Index
TEX4MTXIDX - Texture 4 Matrix Index
TEX5MTXIDX - Texture 5 Matrix Index
TEX6MTXIDX - Texture 6 Matrix Index
TEX7MTXIDX - Texture 7 Matrix Index
POS - Position Vector
NRM - Normal or NBT - Binormal vector (T, B)
CLR0 - Color0 (Diffused)
CLR1 - Color1 (Specular)
TEX0 - Texture 0 data
TEX1 - Texture 1 data
TEX2 - Texture 2 data
TEX3 - Texture 3 data
TEX4 - Texture 4 data
TEX5 - Texture 5 data
TEX6 - Texture 6 data
TEX7 - Texture 7 data

Notice that the Position/Normal and Texture Matrix Indices are different from the other data in that they are 8 bit and must always be sent as direct data.
    5.11.5.2.1  Quads draws a series of non planar quads, using v0,v1,v2,v3 then v4,v5,v6,v7 and so on. (the quad is actually drawn using 2 triangles so the 4 vertices do not have to be coplanar). The minimum number of vertices is 4.
    5.11.5.2.2  Triangles draws a series of triangles, from v0,v1,v2 then v3,v4,v5 and so on. The number of vertices should be a multiple of 3
    5.11.5.2.3  Trianglestrip draws a series of triangles, from v0,v1,v2 then v1,v3,v2, then v2,v3,v4 amd so on. The number of vertices must be at least 3.
    5.11.5.2.4  TriangleFan draws a series of triangles, from v0,v1,v2 then v0,v2,v3 and so on. The number of vertices must be at least 3.
    5.11.5.2.5  Lines draws a series of unconnected lines, from v0 to v1, then from v2 to v3 and so on. The number of vertices should be a multiple of 2
    5.11.5.2.6  Linestrip draws a series of connected lines, from v0 to v1, then from v1 to v2 and so on. If n vertices are drawn, n-1 lines are drawn
    5.11.5.2.7  Points draws a Point at each of the n vertices 5.11.5.3   NOP - No Operation Use it to pad primitive data to 32-byte boundaries and to terminate a display list. 5.11.5.4   CALL DL - Call Display List used to call one display list from another.

8 bits

`7`	`0`
`0100`	`0000`

opcode == 0x40

32 bits

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`0000`	`000.`	`....`	`....`	`....`	`....`	`....`	`....`

list address

32 bits

`31`	`24`	`23`	`16`	`15`	`8`	`7`	`0`
`0000`	`000.`	`....`	`....`	`....`	`....`	`....`	`....`

list size in bytes (32 bit words?)

5.11.5.5 Invalidate Vertex Cache

8 bits

opcode == 0x48

5.11.5.6 BP command (Bypass Raster State Registers)

8 bits	8 bits	24 bits
opcode == 0x61	reg. addr.	reg. value

5.11.5.7 CP command (Command Processor Registers)

8 bits	8 bits	32 bits
opcode == 0x08	reg. addr.	reg. value

5.11.5.8 XF command (Transform Unit Registers)

8 bits	16 bits	16 bits	32 bits * length
opcode == 0x10	length - 1	1st addr.	reg. value(s)

note : "length" is limited to 16.

5.11.5.9 Indexed XF command

8 bits	16 bits	4 bits	12 bits
opcode	index value	length-1	1st address

note : "length" is limited to 16.

There are 4 different XF index units, which are typically used as follows: A: pos. mtx's B: nrm. mtx's C: tex. mtx's D: light obj's.

index